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52 lines
2.1 KiB
Verilog
52 lines
2.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module bin_to_7seg (bin,seg);
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input [3:0] bin;
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output [6:0] seg;
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reg [6:0] seg;
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always @(bin) begin
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case(bin)
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4'h0: seg = 7'b1000000; // output = 0 indicates a lit segment
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4'h1: seg = 7'b1111001; // ---0---
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4'h2: seg = 7'b0100100; // | |
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4'h3: seg = 7'b0110000; // 5 1
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4'h4: seg = 7'b0011001; // | |
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4'h5: seg = 7'b0010010; // ---6---
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4'h6: seg = 7'b0000010; // | |
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4'h7: seg = 7'b1111000; // 4 2
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4'h8: seg = 7'b0000000; // | |
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4'h9: seg = 7'b0011000; // ---3---
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4'ha: seg = 7'b0001000;
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4'hb: seg = 7'b0000011;
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4'hc: seg = 7'b1000110;
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4'hd: seg = 7'b0100001;
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4'he: seg = 7'b0000110;
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4'hf: seg = 7'b0001110;
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default : seg = 7'b1111111;
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endcase
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end
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endmodule
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