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111 lines
3.5 KiB
Verilog
111 lines
3.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-26-2006
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// convert a variable length binary word to hex.
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module bin_to_asc_hex (in,out);
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parameter METHOD = 1;
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parameter WIDTH = 16;
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localparam PAD_BITS = (WIDTH % 4) == 0 ? 0 : (4-(WIDTH%4));
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localparam PADDED_WIDTH = WIDTH + PAD_BITS;
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localparam NYBBLES = PADDED_WIDTH >> 2;
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input [WIDTH-1:0] in;
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output [8*NYBBLES-1:0] out;
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wire [PADDED_WIDTH-1:0] padded_in = {{PAD_BITS {1'b0}},in};
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genvar i;
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generate
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for (i=0; i<NYBBLES; i=i+1)
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begin : h
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wire [3:0] tmp_in = padded_in [4*(i+1)-1:4*i];
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if (METHOD == 0) begin
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// C style comparison.
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wire [7:0] tmp_out;
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assign tmp_out = (tmp_in < 10) ? ("0" | tmp_in) : ("A" + tmp_in - 10);
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assign out [8*(i+1)-1:8*i] = tmp_out;
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end
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else begin
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/////////////////////////////////////
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// METHOD = 1 is an equivalent case
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// statement, to make the minimizations
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// more obvious.
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/////////////////////////////////////
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reg [7:0] tmp_out;
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always @(tmp_in) begin
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case (tmp_in)
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4'h0 : tmp_out = 8'b00110000;
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4'h1 : tmp_out = 8'b00110001;
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4'h2 : tmp_out = 8'b00110010;
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4'h3 : tmp_out = 8'b00110011;
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4'h4 : tmp_out = 8'b00110100;
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4'h5 : tmp_out = 8'b00110101;
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4'h6 : tmp_out = 8'b00110110;
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4'h7 : tmp_out = 8'b00110111;
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4'h8 : tmp_out = 8'b00111000;
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4'h9 : tmp_out = 8'b00111001;
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4'ha : tmp_out = 8'b01000001;
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4'hb : tmp_out = 8'b01000010;
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4'hc : tmp_out = 8'b01000011;
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4'hd : tmp_out = 8'b01000100;
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4'he : tmp_out = 8'b01000101;
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4'hf : tmp_out = 8'b01000110;
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endcase
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end
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assign out [8*(i+1)-1:8*i] = tmp_out;
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end
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end
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endgenerate
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endmodule
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/////////////////////////////////
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// quick sanity check
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/////////////////////////////////
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module bin_to_asc_hex_tb ();
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parameter WIDTH = 16;
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parameter OUT_WIDTH = 4; // Number of nybbles in WIDTH
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reg [WIDTH-1:0] in;
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wire [8*OUT_WIDTH-1:0] oa,ob;
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bin_to_asc_hex a (.in(in),.out(oa));
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bin_to_asc_hex b (.in(in),.out(ob));
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initial begin
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#100000 $stop();
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end
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always begin
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#100 in = $random;
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#100 if (oa !== ob) $display ("Disagreement at time %d",$time);
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end
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endmodule
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