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104 lines
3.0 KiB
Verilog
104 lines
3.0 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module stream_mux #(
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parameter WIDTH = 8
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)
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(
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input clk, arst,
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input [WIDTH-1:0] din_a,
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output din_ready_a,
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input din_valid_a,
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input reporting_a,
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input [WIDTH-1:0] din_b,
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output din_ready_b,
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input din_valid_b,
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input reporting_b,
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input start_harvest,
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output reporting,
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input dout_ready,
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output dout_valid,
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output [WIDTH-1:0] dout
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);
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reg chan_ena;
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reg chan_sel;
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////////////////////////////////////////////
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// MUX A and B ports according to state
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////////////////////////////////////////////
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assign din_ready_a = chan_ena & !chan_sel & dout_ready;
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assign din_ready_b = chan_ena & chan_sel & dout_ready;
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assign dout_valid = (chan_sel ? din_valid_b : din_valid_a);
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assign dout = (chan_sel ? din_b : din_a);
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////////////////////////////////////////////
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// to harvest
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// take report from A then B
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// wait for next harvest
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////////////////////////////////////////////
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reg [2:0] state /* synthesis preserve */;
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localparam ST_IDLE = 0,
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ST_WAIT_A = 1,
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ST_WAIT_NOTA = 2,
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ST_WAIT_B = 3,
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ST_WAIT_NOTB = 4;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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state <= ST_IDLE;
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chan_sel <= 0;
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chan_ena <= 0;
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end
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else begin
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case (state)
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ST_IDLE : begin
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chan_sel <= 0;
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chan_ena <= 0;
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if (start_harvest) state <= ST_WAIT_A;
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end
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ST_WAIT_A : begin
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chan_ena <= 1'b1;
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if (reporting_a) state <= ST_WAIT_NOTA;
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end
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ST_WAIT_NOTA : begin
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if (!reporting_a) state <= ST_WAIT_B;
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end
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ST_WAIT_B : begin
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chan_sel <= 1'b1;
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if (reporting_b) state <= ST_WAIT_NOTB;
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end
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ST_WAIT_NOTB : begin
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if (!reporting_b) state <= ST_IDLE;
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end
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endcase
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end
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end
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assign reporting = (state != ST_IDLE);
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endmodule |