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FPGA
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basic_verilog
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basic_verilog
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benchmark_projects
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gowin_benchmark
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Konstantin Pavlov
f6a5726184
Added reference benchmark project for Gowin IDE
2022-05-16 19:06:38 +03:00
..
dynamic_delay.sv
Added reference benchmark project for Gowin IDE
2022-05-16 19:06:38 +03:00
gowin_benchmark.cst
Added reference benchmark project for Gowin IDE
2022-05-16 19:06:38 +03:00
main.sv
Added reference benchmark project for Gowin IDE
2022-05-16 19:06:38 +03:00
timing.sdc
Added reference benchmark project for Gowin IDE
2022-05-16 19:06:38 +03:00