mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
134 lines
2.6 KiB
Verilog
134 lines
2.6 KiB
Verilog
/*
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Compare KCPSM3 and PacoBlaze3m
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*/
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`define PACOBLAZE3M
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`define PACOBLAZE pacoblaze3m
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`ifndef TEST_FILE
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`define TEST_FILE "../test/uclock.rmh"
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`endif
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`ifndef TEST_CYCLES
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`define TEST_CYCLES 100
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`endif
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`ifndef TEST_IRQ
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`define TEST_IRQ 50
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`endif
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`include "timescale_inc.v"
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`include "pacoblaze_inc.v"
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module compare3m_tb;
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parameter tck = 10, program_cycles = `TEST_CYCLES;
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defparam glbl.ROC_WIDTH = 0;
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reg clk, rst, irq; // clock, reset, interrupt req
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wire [`code_depth-1:0] addr_0, addr_1; // instruction address
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reg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];
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wire [`operand_width-1:0] pid_0, pid_1, pout_0, pout_1; // port id, port out
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wire ren_0, ren_1, wen_0, wen_1, iak_0, iak_1; // read strobe, write strobe, interrupt ack
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wire [`code_width-1:0] din_0, din_1;
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wire [`operand_width-1:0] pin_0 = port_0[pid_0], pin_1 = port_1[pid_1]; // port in
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/* PacoBlaze program memory */
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blockram #(.width(`code_width),.depth(`code_depth)) rom_0(
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.clk(clk),
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.rst(rst),
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.enb(1),
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.wen(0),
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.addr(addr_0),
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.din(0),
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.dout(din_0)
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);
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/* PacoBlaze dut */
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`PACOBLAZE dut_0(
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.clk(clk),
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.reset(rst),
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.address(addr_0),
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.instruction(din_0),
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.port_id(pid_0),
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.read_strobe(ren_0),
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.write_strobe(wen_0),
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.in_port(pin_0),
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.out_port(pout_0),
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.interrupt(irq),
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.interrupt_ack(iak_0)
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);
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/* KCPSM3 program memory */
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blockram #(.width(`code_width),.depth(`code_depth)) rom_1(
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.clk(clk),
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.rst(rst),
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.enb(1),
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.wen(0),
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.addr(addr_1),
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.din(0),
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.dout(din_1)
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);
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/* KCPSM3 dut */
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kcpsm3 dut_1(
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.clk(clk),
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.reset(rst),
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.address(addr_1),
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.instruction(din_1),
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.port_id(pid_1),
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.read_strobe(ren_1),
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.write_strobe(wen_1),
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.in_port(pin_1),
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.out_port(pout_1),
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.interrupt(irq),
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.interrupt_ack(iak_1)
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);
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/* Clocking device */
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always #(tck/2) clk = ~clk;
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/* Watch external ports */
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always @(posedge clk) begin
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if (wen_0) port_0[pid_0] <= pout_0;
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if (wen_1) port_1[pid_1] <= pout_1;
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end
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always @(negedge clk) begin
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$display("%h:%h %h:%h", addr_0, din_0, addr_1, din_1);
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if (addr_0 != addr_1) $display("***address mismatch***");
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end
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/* Simulation setup */
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initial begin
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$dumpvars(-1, compare3m_tb);
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$dumpfile("compare3m_tb.vcd");
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$readmemh(`TEST_FILE, rom_0.ram);
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$readmemh(`TEST_FILE, rom_1.ram);
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end
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/* Simulation */
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integer i;
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initial begin
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/* Initialize port memory */
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for (i=0; i<`port_size; i=i+1) begin
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port_0[i] = i;
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port_1[i] = i;
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end
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clk = 0; rst = 1; irq = 0;
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#(tck*3);
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@(negedge clk) rst = 0; // free processor
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#(tck*`TEST_IRQ);
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@(negedge clk) irq = 1; // flag interrupt
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@(negedge clk) ;
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@(negedge clk) irq = 0;
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#(program_cycles*tck+100) $finish;
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end
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endmodule
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