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257 lines
6.9 KiB
Verilog
257 lines
6.9 KiB
Verilog
/*
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Copyright (C) 2004, 2006 Pablo Bleyer Kocik.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. The name of the author may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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PacoBlaze Arithmetic-Logic Unit.
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*/
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`ifndef PACOBLAZE_ALU_V_
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`define PACOBLAZE_ALU_V_
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`include "pacoblaze_inc.v"
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`ifdef USE_ONEHOT_ENCODING
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`define operation(x) operation[(x)]
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`define operation_is(x) operation[(x)]
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`else
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`define operation(x) (x)
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`define operation_is(x) (operation == (x))
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`endif
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module `PACOBLAZE_ALU(
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operation,
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shift_operation, shift_direction, shift_constant,
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result, operand_a, operand_b,
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`ifdef HAS_WIDE_ALU
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resultw, operand_u, operand_v,
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`endif
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carry_in, zero_out, carry_out
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`ifdef HAS_DEBUG
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, debug
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`endif
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);
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input [`operation_width-1:0] operation; ///< Main operation
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input [2:0] shift_operation; ///< Rotate/shift operation
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input shift_direction; ///< Rotate/shift left(0)/right(1)
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input shift_constant; ///< Shift constant (0 or 1)
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output reg [`operand_width-1:0] result; ///< ALU result
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input [`operand_width-1:0] operand_a, operand_b; ///< ALU operands
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`ifdef HAS_WIDE_ALU
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output reg [`operand_width-1:0] resultw; ///< wide ALU high result
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input [`operand_width-1:0] operand_u, operand_v; ///< wide ALU high operands
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`endif
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input carry_in; ///< Carry in
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output zero_out; ///< Zero out
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output reg carry_out; ///< Carry out
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`ifdef HAS_DEBUG
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output reg [8*`alu_debug_width:1] debug; ///< ALU debug string
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reg [18*8:1] debug_rabc; ///< ALU debug operands and result
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reg [7*8:1] debug_cz; ///< ALU debug flags
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`endif
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/** Adder/substracter second operand. */
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wire [`operand_width-1:0] addsub_b =
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(`operation_is(`op_sub)
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|| `operation_is(`op_subcy)
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`ifdef HAS_COMPARE_OPERATION
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|| `operation_is(`op_compare)
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`endif
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) ? ~operand_b :
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operand_b;
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`ifdef HAS_WIDE_ALU
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wire [2*`operand_width-1:0] addsubw_b =
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(`operation_is(`op_subw) || `operation_is(`op_subwcy)) ? ~{operand_v, operand_b} :
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{operand_v, operand_b};
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`endif
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/** Adder/substracter carry. */
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wire addsub_carry =
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(`operation_is(`op_addcy)
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`ifdef HAS_WIDE_ALU
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|| `operation_is(`op_addwcy)
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`endif
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) ? carry_in :
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(`operation_is(`op_sub)
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`ifdef HAS_COMPARE_OPERATION
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|| `operation_is(`op_compare)
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`endif
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`ifdef HAS_WIDE_ALU
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|| `operation_is(`op_subw)
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`endif
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) ? 1 : // ~b => b'
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(`operation_is(`op_subcy)
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`ifdef HAS_WIDE_ALU
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|| `operation_is(`op_subwcy)
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`endif
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) ? ~carry_in : // ~b - c => b' - c
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0;
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/** Adder/substracter with carry. */
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wire [1+`operand_width-1:0] addsub_result = operand_a + addsub_b + addsub_carry;
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`ifdef HAS_WIDE_ALU
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wire [1+2*`operand_width-1:0] addsubw_result =
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{operand_u, operand_a} + addsubw_b + addsub_carry;
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`endif
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/** Shift bit value. */
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// synthesis parallel_case full_case
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wire shift_bit =
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(shift_operation == `opcode_rr) ? operand_a[0] : // == `opcode_slx
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(shift_operation == `opcode_rl) ? operand_a[7] : // == `opcode_srx
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(shift_operation == `opcode_rsa) ? carry_in :
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shift_constant; // == `opcode_rsc
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`ifdef HAS_WIDE_ALU
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wire [2*`operand_width-1:0] resultx = {resultw, result};
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`endif
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assign zero_out =
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`ifdef HAS_MUL_OPERATION
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(`operation_is(`op_mul)) ? ~|resultx :
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`endif
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`ifdef HAS_WIDE_ALU
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(`operation_is(`op_addw) || `operation_is(`op_addwcy)
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|| `operation_is(`op_subw) || `operation_is(`op_subwcy)
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) ? ~|resultx :
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`endif
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~|result;
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/*
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always @(operation,
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shift_operation, shift_direction, shift_constant, shift_bit,
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result, operand_a, operand_b, carry_in, carry_out,
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addsub_result, addsub_b, addsub_carry
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`ifdef HAS_WIDE_ALU
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, resultw, operand_v, addsubw_result
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`endif
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) begin
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$display("op:%b %h (%h)=(%h),(%h)", operation, operation, result, operand_a, operand_b);
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$display("as:%h=%h+%h+%b", addsub_result, operand_a, addsub_b, addsub_carry);
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end
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*/
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// always @*
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always @(operation,
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shift_operation, shift_direction, shift_constant, shift_bit,
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result, operand_a, operand_b, carry_in, carry_out,
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addsub_result, addsub_carry
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`ifdef HAS_WIDE_ALU
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, resultw, operand_v, addsubw_result
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`endif
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) begin: on_alu
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/* Defaults */
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carry_out = 0;
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`ifdef HAS_WIDE_ALU
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resultw = operand_v;
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`endif
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// synthesis parallel_case full_case
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`ifdef USE_ONEHOT_ENCODING
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case (1'b1)
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`else
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case (operation)
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`endif
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`operation(`op_add),
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`operation(`op_addcy):
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{carry_out, result} = addsub_result;
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`ifdef HAS_COMPARE_OPERATION
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`operation(`op_compare),
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`endif
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`operation(`op_sub),
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`operation(`op_subcy): begin
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{carry_out, result} = {~addsub_result[8], addsub_result[7:0]};
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end
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`operation(`op_and):
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result = operand_a & operand_b;
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`operation(`op_or):
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result = operand_a | operand_b;
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`ifdef HAS_TEST_OPERATION
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`operation(`op_test):
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begin result = operand_a & operand_b; carry_out = ^result; end
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`endif
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`operation(`op_xor):
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result = operand_a ^ operand_b;
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`operation(`op_rs):
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if (shift_direction) // shift right
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{result, carry_out} = {shift_bit, operand_a};
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else // shift left
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{carry_out, result} = {operand_a, shift_bit};
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`ifdef HAS_MUL_OPERATION
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`operation(`op_mul):
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{resultw, result} = operand_a * operand_b;
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`endif
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`ifdef HAS_WIDE_ALU
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`operation(`op_addw),
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`operation(`op_addwcy):
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{carry_out, resultw, result} = addsubw_result;
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`operation(`op_subw),
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`operation(`op_subwcy):
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{carry_out, resultw, result} = {~addsubw_result[16], addsubw_result[15:0]};
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`endif
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default:
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result = operand_b;
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endcase
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end
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`ifdef HAS_DEBUG
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`include "pacoblaze_util.v"
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always @(operand_a, operand_b, result)
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debug_rabc = {"r=", numtohex(result[7:4]), numtohex(operand_a[3:0]), " a=", numtohex(operand_a[7:4]), numtohex(operand_a[3:0]), " b=", numtohex(operand_b[7:4]), numtohex(operand_b[3:0]), " c=", numtohex(carry_in)};
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always @(carry_in, carry_out, zero_out)
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debug_cz = {"C=", numtohex(carry_out), " Z=", numtohex(zero_out)};
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always @(debug_rabc, debug_cz)
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debug = {debug_rabc, ", ", debug_cz};
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`endif // HAS_DEBUG
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endmodule
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`endif // PACOBLAZE_ALU_V_
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