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36 lines
1.7 KiB
Verilog
36 lines
1.7 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module compress_32 (a,b,c,oo,ot);
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parameter WIDTH = 16;
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input [WIDTH-1:0] a,b,c;
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output [WIDTH-1:0] oo,ot;
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genvar i;
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generate
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for (i=0; i<WIDTH; i=i+1)
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begin : cmp
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assign oo[i] = a[i] ^ b[i] ^ c[i];
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assign ot[i] = (a[i] & b[i]) | (a[i] & c[i]) | (b[i] & c[i]);
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end
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endgenerate
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endmodule |