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60 lines
2.1 KiB
Verilog
60 lines
2.1 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 12-17-2008
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// Unrolled descrambler LFSR
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module descrambler # (
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parameter WIDTH = 512
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)(
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input clk,arst,ena,
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input [WIDTH-1:0] din, // bit 0 is used first
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output reg [WIDTH-1:0] dout
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);
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reg [57:0] scram_state;
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wire [WIDTH+58-1:0] history;
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wire [WIDTH-1:0] dout_w;
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assign history = {din,scram_state};
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genvar i;
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generate
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for (i=0; i<WIDTH; i=i+1) begin : lp
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assign dout_w[i] = history[58+i-58] ^ history[58+i-39] ^ history[58+i];
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end
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endgenerate
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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dout <= 0;
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scram_state <= 58'h3ff_ffff_ffff_ffff;
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end
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else if (ena) begin
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dout <= dout_w;
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scram_state <= history[WIDTH+58-1:WIDTH];
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end
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end
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endmodule
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