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101 lines
2.7 KiB
Verilog
101 lines
2.7 KiB
Verilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// BLOCK 4,3
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// baeckler - 12-14-2009
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module gearbox_20_66 (
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input clk,
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input slip_to_frame, // look for ethernet framing, [1:0] opposite
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input [19:0] din, // lsbit used first
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output reg [65:0] dout,
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output reg dout_valid
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);
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wire [21:0] dout_22;
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wire dout_22_valid;
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// framing control
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wire framed = ^dout[1:0];
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reg odd = 1'b0;
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reg drop2 = 1'b0;
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// helper gearbox
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gearbox_20_22 gba (
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.clk(clk),
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.odd(odd),
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.drop2(drop2),
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.din(din), // lsbit used first
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.dout(dout_22),
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.dout_valid(dout_22_valid)
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);
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// combine 3 words of 22 to one 66
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reg [1:0] gbstate = 0 /* synthesis preserve */;
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wire [21:0] dout_mid,dout_low;
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assign {dout_mid,dout_low} = dout[43:0];
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always @(posedge clk) begin
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dout_valid <= 1'b0;
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drop2 <= 1'b0;
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case (gbstate)
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2'h0 : begin
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if (dout_22_valid) begin
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dout <= {22'h0,22'h0,dout_22};
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gbstate <= 2'h1;
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end
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end
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2'h1 : begin
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if (slip_to_frame & !framed) begin
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if (!odd) odd <= 1'b1;
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else begin
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drop2 <= 1'b1;
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odd <= 1'b0;
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end
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end
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if (dout_22_valid) begin
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dout <= {22'h0,dout_22,dout_low};
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gbstate <= 2'h2;
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end
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end
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2'h2 : begin
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if (dout_22_valid) begin
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dout <= {dout_22,dout_mid,dout_low};
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gbstate <= 2'h0;
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dout_valid <= 1'b1;
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end
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end
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2'h3 : begin
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// this is an illegal state. Recover
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gbstate <= 2'h0;
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end
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endcase
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end
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endmodule |