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78 lines
2.6 KiB
Verilog
78 lines
2.6 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 06-12-2007
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module seconds_counter (clk100,reset,count_val,tick);
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parameter WIDTH = 10;
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input clk100,reset;
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output [WIDTH-1:0] count_val;
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output tick;
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// divide by 1000
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reg [9:0] div_one;
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reg div_one_max;
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always @(posedge clk100) begin
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div_one_max <= (div_one == 10'd998);
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if (div_one_max | reset) div_one <= 10'd0;
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else div_one <= div_one + 1'b1;
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end
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// divide by 1000
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reg [9:0] div_two;
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reg div_two_max;
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always @(posedge clk100) begin
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div_two_max <= (div_two == 10'd999);
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if ((div_one_max & div_two_max) | reset) div_two <= 10'd0;
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else if (div_one_max) div_two <= div_two + 1'b1;
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end
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// divide by 100
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reg [6:0] div_three;
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reg div_three_max;
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always @(posedge clk100) begin
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div_three_max <= (div_three == 7'd99);
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if ((div_one_max & div_two_max & div_three_max) | reset) div_three <= 10'd0;
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else if (div_one_max & div_two_max) div_three <= div_three + 1'b1;
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end
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// tally seconds
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reg tick, reset_pending;
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reg [WIDTH-1:0] count_val;
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always @(posedge clk100) begin
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reset_pending <= reset;
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tick <= div_one_max & div_two_max & div_three_max & !reset_pending & !reset;
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if (reset | reset_pending) begin
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count_val <= 0;
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end
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else if (tick) begin
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count_val <= count_val + 1'b1;
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end
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end
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endmodule |