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110 lines
3.2 KiB
Verilog
110 lines
3.2 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 11-06-2008
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// pipeline for ready / valid data
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module ready_skid #(
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parameter WIDTH = 16
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)
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(
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input clk,arst,
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input valid_i,
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input [WIDTH-1:0] dat_i,
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output reg ready_i,
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output reg valid_o,
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output reg [WIDTH-1:0] dat_o,
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input ready_o
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);
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reg [WIDTH-1:0] backup_storage;
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reg backup_valid;
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// duplicate control registers to mitigate
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// high fanout loading.
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reg internal_valid_o /* synthesis preserve */;
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reg internal_ready_i /* synthesis preserve */;
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// simulation only sanity check
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always @(posedge clk) begin
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if ((ready_i != internal_ready_i) ||
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(valid_o != internal_valid_o)) begin
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$display ("Error: Duplicate internal regs out of sync");
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end
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end
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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ready_i <= 1'b0;
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internal_ready_i <= 1'b0;
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valid_o <= 1'b0;
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internal_valid_o <= 1'b0;
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dat_o <= 0;
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backup_storage <= 0;
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backup_valid <= 1'b0;
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end
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else begin
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ready_i <= ready_o;
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internal_ready_i <= ready_o;
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if (internal_valid_o & ready_o) begin
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// main data is leaving to the sink
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if (backup_valid) begin
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// dump the backup word to main storage
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backup_valid <= 1'b0;
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dat_o <= backup_storage;
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valid_o <= 1'b1;
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internal_valid_o <= 1'b1;
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if (ready_i && valid_i) begin
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$display ("ERROR: data lost in skid buffer");
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end
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end
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else begin
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// if not overwritten below, you are done.
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valid_o <= 1'b0;
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internal_valid_o <= 1'b0;
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end
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end
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if (internal_ready_i && valid_i) begin
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// must accept data from source
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if (ready_o || !internal_valid_o) begin
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// accept to main registers
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valid_o <= 1'b1;
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internal_valid_o <= 1'b1;
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dat_o <= dat_i;
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end
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else begin
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// accept to backup storage
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backup_valid <= 1'b1;
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backup_storage <= dat_i;
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ready_i <= 1'b0; // stop stop!
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internal_ready_i <= 1'b0;
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end
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end
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end
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end
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endmodule
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