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106 lines
2.9 KiB
Verilog
106 lines
2.9 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module ycbcr_to_rgb_tb ();
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reg rst,clk;
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reg [7:0] y,cb,cr;
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wire [7:0] red,green,blue;
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///////////////////////////////////////////
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// test device
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ycbcr_to_rgb dut (
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.y(y),.cb(cb),.cr(cr),
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.red(red),.green(green),.blue(blue),
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.clk(clk)
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);
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///////////////////////////////////////////
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// reference formulas
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real r,rp,rpp,g,gp,gpp,b,bp,bpp;
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real ry,rcr,rcb;
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real c16 = 16; // A Verilog type cast?
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real c128 = 128;
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always @(posedge clk) begin
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ry <= y-c16;
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rcr <= cr-c128;
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rcb <= cb-c128;
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rpp <= 1.164 * ry + 1.596 * rcr;
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gpp <= 1.164 * ry - 0.813 * rcr - 0.392*rcb;
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bpp <= 1.164 * ry + 2.017 * rcb;
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rp <= rpp;
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gp <= gpp;
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bp <= bpp;
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r <= (rp < 0) ? 0 : (rp > 255) ? 255 : rp;
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g <= (gp < 0) ? 0 : (gp > 255) ? 255 : gp;
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b <= (bp < 0) ? 0 : (bp > 255) ? 255 : bp;
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end
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real error_bar = 2;
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real rdelta,gdelta,bdelta;
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integer n = 0;
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initial begin
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clk = 0;
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rst = 0;
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@(negedge clk) y = 255; cb = 255; cr = 255;
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@(negedge clk); @(negedge clk);
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@(negedge clk) y = 255; cb = 0; cr = 0;
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@(negedge clk); @(negedge clk);
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for (n=0; n<1000000; n=n+1)
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begin
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@(negedge clk) y = $random; cb = $random; cr = $random;
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@(negedge clk);
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@(negedge clk);
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rdelta = r-red;
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gdelta = g-green;
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bdelta = b-blue;
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if ((rdelta > error_bar) |
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(rdelta < -error_bar) |
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(gdelta > error_bar) |
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(gdelta < -error_bar) |
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(bdelta > error_bar) |
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(bdelta < -error_bar))
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begin
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$display ("Error margin too high at time %d", $time);
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#100
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$stop();
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end
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end
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$display ("PASS");
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$stop();
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end
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always begin
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#50 clk = ~clk;
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end
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endmodule
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