FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
basic_verilog/scripts/mem_writer_examples/16x8bit_linear.mem
Konstantin Pavlov c6d4f60bca Updated mem_writer scripts and example output
2022-04-05 18:39:41 +03:00

17 lines
32 B
Plaintext
Raw Blame History

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Reference in New Issue View Git Blame Copy Permalink