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200 lines
7.0 KiB
Verilog
200 lines
7.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//// CRC-16 of 8 data bits. MSB used first.
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// Polynomial 00001021 (MSB excluded)
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// x^12 + x^5 + x^0
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//
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// Optimal LUT depth 2
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//
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// CCCCCCCCCCCCCCCC DDDDDDDD
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// 0000000000111111 00000000
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// 0123456789012345 01234567
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//
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// C00 = ........X...X... X...X...
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// C01 = .........X...X.. .X...X..
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// C02 = ..........X...X. ..X...X.
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// C03 = ...........X...X ...X...X
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// C04 = ............X... ....X...
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// C05 = ........X...XX.. X...XX..
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// C06 = .........X...XX. .X...XX.
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// C07 = ..........X...XX ..X...XX
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// C08 = X..........X...X ...X...X
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// C09 = .X..........X... ....X...
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// C10 = ..X..........X.. .....X..
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// C11 = ...X..........X. ......X.
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// C12 = ....X...X...X..X X...X..X
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// C13 = .....X...X...X.. .X...X..
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// C14 = ......X...X...X. ..X...X.
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// C15 = .......X...X...X ...X...X
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//
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module crc16_dat8 (crc_in,dat_in,crc_out);
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input [15:0] crc_in;
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input [7:0] dat_in;
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output [15:0] crc_out;
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wire [15:0] crc_out;
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parameter METHOD = 1;
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generate
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if (METHOD == 0)
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crc16_dat8_flat cc (.crc_in(crc_in),.dat_in(dat_in),.crc_out(crc_out));
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else
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crc16_dat8_factor cc (.crc_in(crc_in),.dat_in(dat_in),.crc_out(crc_out));
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endgenerate
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endmodule
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////////////////////////////////////////////////////////////////
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// Flat version
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////////////////////////////////////////////////////////////////
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module crc16_dat8_flat (crc_in,dat_in,crc_out);
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input [15:0] crc_in;
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input [7:0] dat_in;
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output [15:0] crc_out;
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wire [15:0] crc_out;
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wire x7, x6, x5, x4, x3, x2, x1,
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x0, x15, x14, x13, x12, x11, x10, x9,
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x8;
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assign crc_out = {x15,x14,x13,x12,x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
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x0};
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wire d0,d1,d2,d3,d4,d5,d6,d7;
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assign { d7,d6,d5,d4,d3,d2,d1,d0} = dat_in [7:0];
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wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,
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c15;
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assign { c15,c14,c13,c12,c11,c10,c9,c8,c7,c6,c5,c4,c3,c2,c1,
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c0} = crc_in [15:0];
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xor6 x7i (.out(x7),.a(c10),.b(d6),.c(c14),.d(d2),.e(c15),.f(d7)); // 6 ins 1 outs
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xor6 x6i (.out(x6),.a(c9),.b(d5),.c(c13),.d(d1),.e(c14),.f(d6)); // 6 ins 1 outs
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xor6 x5i (.out(x5),.a(c8),.b(d4),.c(c12),.d(d0),.e(c13),.f(d5)); // 6 ins 1 outs
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xor6 x4i (.out(x4),.a(c12),.b(d4),.c(1'b0),.d(1'b0),.e(1'b0),.f(1'b0)); // 2 ins 1 outs
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xor6 x3i (.out(x3),.a(c11),.b(d7),.c(c15),.d(d3),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x2i (.out(x2),.a(c10),.b(d6),.c(c14),.d(d2),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x1i (.out(x1),.a(c9),.b(d5),.c(c13),.d(d1),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x0i (.out(x0),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x15i (.out(x15),.a(c11),.b(d7),.c(c15),.d(d3),.e(c7),.f(1'b0)); // 5 ins 1 outs
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xor6 x14i (.out(x14),.a(c10),.b(d6),.c(c14),.d(d2),.e(c6),.f(1'b0)); // 5 ins 1 outs
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xor6 x13i (.out(x13),.a(c9),.b(d5),.c(c13),.d(d1),.e(c5),.f(1'b0)); // 5 ins 1 outs
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assign x12 = c8 ^ d4 ^ c12 ^ d0 ^ c15 ^ d7 ^ c4; // 7 ins 1 outs
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xor6 x11i (.out(x11),.a(c14),.b(d6),.c(c3),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x10i (.out(x10),.a(c13),.b(d5),.c(c2),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x9i (.out(x9),.a(c12),.b(d4),.c(c1),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x8i (.out(x8),.a(c11),.b(d7),.c(c15),.d(d3),.e(c0),.f(1'b0)); // 5 ins 1 outs
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endmodule
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////////////////////////////////////////////////////////////////
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// Depth optimal factored version
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////////////////////////////////////////////////////////////////
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module crc16_dat8_factor (crc_in,dat_in,crc_out);
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input [15:0] crc_in;
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input [7:0] dat_in;
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output [15:0] crc_out;
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wire [15:0] crc_out;
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wire x19, x18, x17, x16, x7, x6, x5,
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x4, x3, x2, x1, x0, x15, x14, x13,
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x12, x11, x10, x9, x8;
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assign crc_out = {x15,x14,x13,x12,x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
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x0};
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wire d0,d1,d2,d3,d4,d5,d6,d7;
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assign { d7,d6,d5,d4,d3,d2,d1,d0} = dat_in [7:0];
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wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,
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c15;
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assign { c15,c14,c13,c12,c11,c10,c9,c8,c7,c6,c5,c4,c3,c2,c1,
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c0} = crc_in [15:0];
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xor6 x19i (.out(x19),.a(c7),.b(c11),.c(c15),.d(d7),.e(d3),.f(1'b0)); // 5 ins 2 outs
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xor6 x18i (.out(x18),.a(c5),.b(d1),.c(c9),.d(c13),.e(d5),.f(1'b0)); // 5 ins 2 outs
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xor6 x17i (.out(x17),.a(c6),.b(c10),.c(d6),.d(c14),.e(d2),.f(1'b0)); // 5 ins 2 outs
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xor6 x16i (.out(x16),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0)); // 4 ins 2 outs
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xor6 x7i (.out(x7),.a(x17),.b(c6),.c(c15),.d(d7),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x6i (.out(x6),.a(d6),.b(c14),.c(x18),.d(c5),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x5i (.out(x5),.a(x16),.b(c13),.c(d5),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x4i (.out(x4),.a(c12),.b(d4),.c(1'b0),.d(1'b0),.e(1'b0),.f(1'b0)); // 2 ins 1 outs
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xor6 x3i (.out(x3),.a(c11),.b(d7),.c(c15),.d(d3),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x2i (.out(x2),.a(c10),.b(d6),.c(c14),.d(d2),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x1i (.out(x1),.a(c9),.b(d5),.c(c13),.d(d1),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x0i (.out(x0),.a(c8),.b(d4),.c(c12),.d(d0),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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assign x15 = x19; // 1 ins 1 outs
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assign x14 = x17; // 1 ins 1 outs
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assign x13 = x18; // 1 ins 1 outs
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xor6 x12i (.out(x12),.a(x16),.b(c15),.c(d7),.d(c4),.e(1'b0),.f(1'b0)); // 4 ins 1 outs
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xor6 x11i (.out(x11),.a(c14),.b(d6),.c(c3),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x10i (.out(x10),.a(c13),.b(d5),.c(c2),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x9i (.out(x9),.a(c12),.b(d4),.c(c1),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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xor6 x8i (.out(x8),.a(x19),.b(c7),.c(c0),.d(1'b0),.e(1'b0),.f(1'b0)); // 3 ins 1 outs
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endmodule
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