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198 lines
7.0 KiB
Verilog
198 lines
7.0 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//
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// 32 bit CRC of 31 data bits (forward - LSB first)
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// polynomial : 00a00805
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// x^23 + x^21 + x^11 + x^2 + x^0
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//
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// CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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// 00000000001111111111222222222233 0000000000111111111122222222223
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// 01234567890123456789012345678901 0123456789012345678901234567890
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// C00 = .#........#.#......#..##....#.## ...............................
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// C01 = ..#........#.#......#..##....#.# ...............................
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// C02 = .#.#......#...#....#.#####..#..# ...............................
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// C03 = ..#.#......#...#....#.#####..#.. ...............................
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// C04 = ...#.#......#...#....#.#####..#. ...............................
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// C05 = ....#.#......#...#....#.#####..# ...............................
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// C06 = .....#.#......#...#....#.#####.. ...............................
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// C07 = ......#.#......#...#....#.#####. ...............................
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// C08 = .......#.#......#...#....#.##### ...............................
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// C09 = ........#.#......#...#....#.#### ...............................
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// C10 = .........#.#......#...#....#.### ...............................
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// C11 = .#....................#......... ...............................
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// C12 = ..#....................#........ ...............................
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// C13 = ...#....................#....... ...............................
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// C14 = ....#....................#...... ...............................
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// C15 = .....#....................#..... ...............................
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// C16 = ......#....................#.... ...............................
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// C17 = .......#....................#... ...............................
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// C18 = ........#....................#.. ...............................
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// C19 = .........#....................#. ...............................
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// C20 = ..........#....................# ...............................
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// C21 = .#........###......#..##....#.## ...............................
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// C22 = ..#........###......#..##....#.# ...............................
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// C23 = .#.#......#..##....#.#####..#..# ...............................
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// C24 = ..#.#......#..##....#.#####..#.. ...............................
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// C25 = ...#.#......#..##....#.#####..#. ...............................
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// C26 = ....#.#......#..##....#.#####..# ...............................
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// C27 = .....#.#......#..##....#.#####.. ...............................
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// C28 = ......#.#......#..##....#.#####. ...............................
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// C29 = .......#.#......#..##....#.##### ...............................
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// C30 = ........#.#......#..##....#.#### ...............................
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// C31 = #........#.#......#..##....#.### ...............................
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//
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// Number of XORs used is 32
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// Maximum XOR input count is 13
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// Best possible depth in 4 LUTs = 2
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// Best possible depth in 5 LUTs = 2
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// Best possible depth in 6 LUTs = 2
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// Total XOR inputs 250
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//
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module fec_rot_31 (
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input [31:0] c,
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output [31:0] co
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);
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assign co[0] =
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c[1] ^ c[10] ^ c[12] ^ c[19] ^ c[22] ^ c[23] ^
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c[28] ^ c[30] ^ c[31];
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assign co[1] =
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c[2] ^ c[11] ^ c[13] ^ c[20] ^ c[23] ^ c[24] ^
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c[29] ^ c[31];
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assign co[2] =
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c[1] ^ c[3] ^ c[10] ^ c[14] ^ c[19] ^ c[21] ^
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c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[31];
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assign co[3] =
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c[2] ^ c[4] ^ c[11] ^ c[15] ^ c[20] ^ c[22] ^
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c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[29];
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assign co[4] =
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c[3] ^ c[5] ^ c[12] ^ c[16] ^ c[21] ^ c[23] ^
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c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[30];
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assign co[5] =
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c[4] ^ c[6] ^ c[13] ^ c[17] ^ c[22] ^ c[24] ^
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c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
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assign co[6] =
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c[5] ^ c[7] ^ c[14] ^ c[18] ^ c[23] ^ c[25] ^
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c[26] ^ c[27] ^ c[28] ^ c[29];
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assign co[7] =
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c[6] ^ c[8] ^ c[15] ^ c[19] ^ c[24] ^ c[26] ^
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c[27] ^ c[28] ^ c[29] ^ c[30];
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assign co[8] =
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c[7] ^ c[9] ^ c[16] ^ c[20] ^ c[25] ^ c[27] ^
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c[28] ^ c[29] ^ c[30] ^ c[31];
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assign co[9] =
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c[8] ^ c[10] ^ c[17] ^ c[21] ^ c[26] ^ c[28] ^
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c[29] ^ c[30] ^ c[31];
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assign co[10] =
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c[9] ^ c[11] ^ c[18] ^ c[22] ^ c[27] ^ c[29] ^
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c[30] ^ c[31];
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assign co[11] =
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c[1] ^ c[22];
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assign co[12] =
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c[2] ^ c[23];
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assign co[13] =
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c[3] ^ c[24];
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assign co[14] =
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c[4] ^ c[25];
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assign co[15] =
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c[5] ^ c[26];
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assign co[16] =
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c[6] ^ c[27];
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assign co[17] =
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c[7] ^ c[28];
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assign co[18] =
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c[8] ^ c[29];
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assign co[19] =
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c[9] ^ c[30];
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assign co[20] =
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c[10] ^ c[31];
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assign co[21] =
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c[1] ^ c[10] ^ c[11] ^ c[12] ^ c[19] ^ c[22] ^
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c[23] ^ c[28] ^ c[30] ^ c[31];
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assign co[22] =
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c[2] ^ c[11] ^ c[12] ^ c[13] ^ c[20] ^ c[23] ^
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c[24] ^ c[29] ^ c[31];
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assign co[23] =
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c[1] ^ c[3] ^ c[10] ^ c[13] ^ c[14] ^ c[19] ^
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c[21] ^ c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[28] ^ c[31];
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assign co[24] =
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c[2] ^ c[4] ^ c[11] ^ c[14] ^ c[15] ^ c[20] ^
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c[22] ^ c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[29];
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assign co[25] =
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c[3] ^ c[5] ^ c[12] ^ c[15] ^ c[16] ^ c[21] ^
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c[23] ^ c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[30];
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assign co[26] =
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c[4] ^ c[6] ^ c[13] ^ c[16] ^ c[17] ^ c[22] ^
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c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
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assign co[27] =
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c[5] ^ c[7] ^ c[14] ^ c[17] ^ c[18] ^ c[23] ^
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c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29];
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assign co[28] =
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c[6] ^ c[8] ^ c[15] ^ c[18] ^ c[19] ^ c[24] ^
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c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
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assign co[29] =
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c[7] ^ c[9] ^ c[16] ^ c[19] ^ c[20] ^ c[25] ^
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c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
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assign co[30] =
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c[8] ^ c[10] ^ c[17] ^ c[20] ^ c[21] ^ c[26] ^
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c[28] ^ c[29] ^ c[30] ^ c[31];
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assign co[31] =
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c[0] ^ c[9] ^ c[11] ^ c[18] ^ c[21] ^ c[22] ^
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c[27] ^ c[29] ^ c[30] ^ c[31];
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endmodule
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