mirror of
https://github.com/pConst/basic_verilog.git
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401 lines
11 KiB
Verilog
401 lines
11 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 08-25-2006
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//////////////////////////////////////////
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// 32 bit to 39 bit ECC encoder
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//////////////////////////////////////////
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module ecc_encode_32bit (d,c);
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input [31:0] d;
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output [38:0] c;
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wire [38:0] c;
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wire [2:0] help_c0;
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xor6 help_c0_0 (help_c0[0],d[0],d[1],d[3],d[4],d[6],d[8]);
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xor6 help_c0_1 (help_c0[1],d[10],d[11],d[13],d[15],d[17],d[19]);
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xor6 help_c0_2 (help_c0[2],d[21],d[23],d[25],d[26],d[28],d[30]);
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assign c[0] = ^help_c0;
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wire [2:0] help_c1;
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xor6 help_c1_0 (help_c1[0],d[0],d[2],d[3],d[5],d[6],d[9]);
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xor6 help_c1_1 (help_c1[1],d[10],d[12],d[13],d[16],d[17],d[20]);
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xor6 help_c1_2 (help_c1[2],d[21],d[24],d[25],d[27],d[28],d[31]);
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assign c[1] = ^help_c1;
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assign c[2] = d[0];
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wire [2:0] help_c3;
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xor6 help_c3_0 (help_c3[0],d[1],d[2],d[3],d[7],d[8],d[9]);
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xor6 help_c3_1 (help_c3[1],d[10],d[14],d[15],d[16],d[17],d[22]);
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xor6 help_c3_2 (help_c3[2],d[23],d[24],d[25],d[29],d[30],d[31]);
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assign c[3] = ^help_c3;
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assign c[4] = d[1];
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assign c[5] = d[2];
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assign c[6] = d[3];
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wire [2:0] help_c7;
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xor6 help_c7_0 (help_c7[0],d[4],d[5],d[6],d[7],d[8],d[9]);
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xor6 help_c7_1 (help_c7[1],d[10],d[18],d[19],d[20],d[21],d[22]);
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xor6 help_c7_2 (help_c7[2],d[23],d[24],d[25],1'b0,1'b0,1'b0);
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assign c[7] = ^help_c7;
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assign c[8] = d[4];
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assign c[9] = d[5];
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assign c[10] = d[6];
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assign c[11] = d[7];
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assign c[12] = d[8];
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assign c[13] = d[9];
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assign c[14] = d[10];
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wire [2:0] help_c15;
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xor6 help_c15_0 (help_c15[0],d[11],d[12],d[13],d[14],d[15],d[16]);
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xor6 help_c15_1 (help_c15[1],d[17],d[18],d[19],d[20],d[21],d[22]);
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xor6 help_c15_2 (help_c15[2],d[23],d[24],d[25],1'b0,1'b0,1'b0);
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assign c[15] = ^help_c15;
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assign c[16] = d[11];
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assign c[17] = d[12];
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assign c[18] = d[13];
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assign c[19] = d[14];
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assign c[20] = d[15];
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assign c[21] = d[16];
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assign c[22] = d[17];
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assign c[23] = d[18];
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assign c[24] = d[19];
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assign c[25] = d[20];
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assign c[26] = d[21];
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assign c[27] = d[22];
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assign c[28] = d[23];
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assign c[29] = d[24];
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assign c[30] = d[25];
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wire [0:0] help_c31;
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xor6 help_c31_0 (help_c31[0],d[26],d[27],d[28],d[29],d[30],d[31]);
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assign c[31] = ^help_c31;
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assign c[32] = d[26];
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assign c[33] = d[27];
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assign c[34] = d[28];
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assign c[35] = d[29];
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assign c[36] = d[30];
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assign c[37] = d[31];
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wire [2:0] help_c38;
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xor6 help_c38_0 (help_c38[0],d[0],d[1],d[2],d[4],d[5],d[7]);
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xor6 help_c38_1 (help_c38[1],d[10],d[11],d[12],d[14],d[17],d[18]);
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xor6 help_c38_2 (help_c38[2],d[21],d[23],d[24],d[26],d[27],d[29]);
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assign c[38] = ^help_c38;
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endmodule
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//////////////////////////////////////////
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// compute a syndrome from the code word
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//////////////////////////////////////////
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module ecc_syndrome_32bit (clk,rst,c,s);
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// optional register on the outputs
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// of bits 0..6 and back one level in bit 7
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parameter REGISTER = 0;
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input clk,rst;
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input [38:0] c;
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output [6:0] s;
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reg [6:0] s;
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// 19 terms
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wire [3:0] help_s0;
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xor6 help_s0_0 (help_s0[0],c[0],c[2],c[4],c[6],c[8],c[10]);
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xor6 help_s0_1 (help_s0[1],c[12],c[14],c[16],c[18],c[20],c[22]);
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xor6 help_s0_2 (help_s0[2],c[24],c[26],c[28],c[30],c[32],c[34]);
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assign help_s0[3] = c[36];
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[0] <= 0;
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else s[0] <= ^help_s0;
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end
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end else begin
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always @(help_s0) begin
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s[0] = ^help_s0;
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end
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end
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endgenerate
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// 19 terms
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wire [3:0] help_s1;
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xor6 help_s1_0 (help_s1[0],c[1],c[2],c[5],c[6],c[9],c[10]);
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xor6 help_s1_1 (help_s1[1],c[13],c[14],c[17],c[18],c[21],c[22]);
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xor6 help_s1_2 (help_s1[2],c[25],c[26],c[29],c[30],c[33],c[34]);
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assign help_s1[3] = c[37];
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[1] <= 0;
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else s[1] <= ^help_s1;
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end
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end else begin
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always @(help_s1) begin
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s[1] = ^help_s1;
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end
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end
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endgenerate
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// 19 terms
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wire [3:0] help_s2;
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xor6 help_s2_0 (help_s2[0],c[3],c[4],c[5],c[6],c[11],c[12]);
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xor6 help_s2_1 (help_s2[1],c[13],c[14],c[19],c[20],c[21],c[22]);
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xor6 help_s2_2 (help_s2[2],c[27],c[28],c[29],c[30],c[35],c[36]);
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assign help_s2[3] = c[37];
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[2] <= 0;
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else s[2] <= ^help_s2;
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end
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end else begin
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always @(help_s2) begin
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s[2] = ^help_s2;
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end
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end
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endgenerate
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// 16 terms
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wire [2:0] help_s3;
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xor6 help_s3_0 (help_s3[0],c[7],c[8],c[9],c[10],c[11],c[12]);
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xor6 help_s3_1 (help_s3[1],c[13],c[14],c[23],c[24],c[25],c[26]);
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xor6 help_s3_2 (help_s3[2],c[27],c[28],c[29],c[30],1'b0,1'b0);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[3] <= 0;
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else s[3] <= ^help_s3;
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end
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end else begin
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always @(help_s3) begin
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s[3] = ^help_s3;
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end
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end
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endgenerate
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// 16 terms
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wire [2:0] help_s4;
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xor6 help_s4_0 (help_s4[0],c[15],c[16],c[17],c[18],c[19],c[20]);
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xor6 help_s4_1 (help_s4[1],c[21],c[22],c[23],c[24],c[25],c[26]);
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xor6 help_s4_2 (help_s4[2],c[27],c[28],c[29],c[30],1'b0,1'b0);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[4] <= 0;
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else s[4] <= ^help_s4;
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end
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end else begin
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always @(help_s4) begin
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s[4] = ^help_s4;
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end
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end
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endgenerate
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// 7 terms
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wire [1:0] help_s5;
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xor6 help_s5_0 (help_s5[0],c[31],c[32],c[33],c[34],c[35],c[36]);
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assign help_s5[1] = c[37];
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[5] <= 0;
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else s[5] <= ^help_s5;
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end
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end else begin
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always @(help_s5) begin
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s[5] = ^help_s5;
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end
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end
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endgenerate
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// 39 terms
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wire [6:0] help_s6;
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xor6 help_s6_0 (help_s6[0],c[0],c[1],c[2],c[3],c[4],c[5]);
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xor6 help_s6_1 (help_s6[1],c[6],c[7],c[8],c[9],c[10],c[11]);
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xor6 help_s6_2 (help_s6[2],c[12],c[13],c[14],c[15],c[16],c[17]);
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xor6 help_s6_3 (help_s6[3],c[18],c[19],c[20],c[21],c[22],c[23]);
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xor6 help_s6_4 (help_s6[4],c[24],c[25],c[26],c[27],c[28],c[29]);
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xor6 help_s6_5 (help_s6[5],c[30],c[31],c[32],c[33],c[34],c[35]);
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xor6 help_s6_6 (help_s6[6],c[36],c[37],c[38],1'b0,1'b0,1'b0);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[6] <= 0;
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else s[6] <= ^help_s6;
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end
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end else begin
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always @(help_s6) begin
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s[6] = ^help_s6;
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end
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end
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endgenerate
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endmodule
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//////////////////////////////////////////
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// From the syndrome compute the correction
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// needed to fix the data, or set fatal = 1
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// and no correction if there are too many.
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//////////////////////////////////////////
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module ecc_correction_32bit (s,e,fatal);
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input [6:0] s;
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output [31:0] e;
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output fatal;
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wire [31:0] e;
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// decode the syndrome
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reg [127:0] d;
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wire [127:0] dw /* synthesis keep */;
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always @(s) begin
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d = 128'b0;
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d[{!s[6],s[5:0]}] = 1'b1;
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end
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assign dw = d;
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// Identify uncorrectable errors
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wire fatal = (|s[5:0]) & !s[6] /* synthesis keep */;
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assign e = {
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dw[38],dw[37],dw[36],dw[35],
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dw[34],dw[33],dw[31],dw[30],
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dw[29],dw[28],dw[27],dw[26],
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dw[25],dw[24],dw[23],dw[22],
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dw[21],dw[20],dw[19],dw[18],
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dw[17],dw[15],dw[14],dw[13],
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dw[12],dw[11],dw[10],dw[9],
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dw[7],dw[6],dw[5],dw[3]
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};
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endmodule
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//////////////////////////////////////////
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// select the (uncorrected) data bits out
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// of the code word.
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//////////////////////////////////////////
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module ecc_raw_data_32bit (clk,rst,c,d);
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parameter REGISTER = 0;
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input clk,rst;
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input [38:0] c;
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output [31:0] d;
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reg [31:0] d;
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wire [31:0] d_int;
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// pull out the pure data bits
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assign d_int = {
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c[37],c[36],c[35],c[34],c[33],c[32],c[30],c[29],
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c[28],c[27],c[26],c[25],c[24],c[23],c[22],c[21],
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c[20],c[19],c[18],c[17],c[16],c[14],c[13],c[12],
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c[11],c[10],c[9],c[8],c[6],c[5],c[4],c[2]
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};
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// conditional output register
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) d <= 0;
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else d <= d_int;
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end
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end else begin
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always @(d_int) begin
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d <= d_int;
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end
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end
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endgenerate
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endmodule
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//////////////////////////////////////////
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// 39 bit to 32 bit ECC decoder
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//////////////////////////////////////////
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module ecc_decode_32bit (clk,rst,c,d,no_err,err_corrected,err_fatal);
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// optional pipeline registers at the halfway
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// point and on the outputs
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parameter MIDDLE_REG = 0;
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parameter OUTPUT_REG = 0;
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input clk,rst;
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input [38:0] c;
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output [31:0] d;
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output no_err, err_corrected, err_fatal;
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reg [31:0] d;
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reg no_err, err_corrected, err_fatal;
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// Pull the raw (uncorrected) data from the codeword
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wire [31:0] raw_bits;
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ecc_raw_data_32bit raw (.clk(clk),.rst(rst),.c(c),.d(raw_bits));
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defparam raw .REGISTER = MIDDLE_REG;
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// Build syndrome, which will be 0 for correct
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// correct codewords, otherwise a pointer to the
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// error.
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wire [6:0] syndrome;
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ecc_syndrome_32bit syn (.clk(clk),.rst(rst),.c(c),.s(syndrome));
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defparam syn .REGISTER = MIDDLE_REG;
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// Use the the syndrome to find a correction, or 0 for no correction
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wire [31:0] err_flip;
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wire fatal;
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ecc_correction_32bit cor (.s(syndrome),.e(err_flip),.fatal(fatal));
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// Classify error types and correct data as appropriate
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// If there is a multibit error take care not to make
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// the data worse.
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generate
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if (OUTPUT_REG) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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no_err <= 1'b0;
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err_corrected <= 1'b0;
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err_fatal <= 1'b0;
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d <= 1'b0;
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end else begin
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no_err <= ~| syndrome;
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err_corrected <= syndrome[6];
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err_fatal <= fatal;
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d <= err_flip ^ raw_bits;
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end
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end
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end else begin
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always @(*) begin
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no_err = ~| syndrome;
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err_corrected = syndrome[6];
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err_fatal = fatal;
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d = err_flip ^ raw_bits;
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end
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end
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endgenerate
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endmodule
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