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139 lines
3.8 KiB
Verilog
139 lines
3.8 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-28-2008
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module chain_delay_race
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(
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clk,rst,
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calibrate_a,
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calibrate_b,
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a_wins,
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b_wins,
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valid
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);
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parameter CHAIN_LEN = 32;
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parameter CALIBRATE_BITS = 4;
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localparam CALIBRATE_DEC = (1<<CALIBRATE_BITS);
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input clk,rst;
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input [CALIBRATE_BITS-1:0] calibrate_a;
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input [CALIBRATE_BITS-1:0] calibrate_b;
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output a_wins,b_wins,valid;
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reg flush, valid;
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///////////////////////
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// input regs
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///////////////////////
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reg [CALIBRATE_BITS-1:0] calibrate_a_r /* synthesis preserve */;
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reg [CALIBRATE_BITS-1:0] calibrate_b_r /* synthesis preserve */;
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always @(posedge clk) begin
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if (rst) begin
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calibrate_a_r <= 0;
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calibrate_b_r <= 0;
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end
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else begin
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calibrate_a_r <= calibrate_a;
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calibrate_b_r <= calibrate_b;
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end
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end
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///////////////////////
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// path A
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///////////////////////
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reg [CALIBRATE_DEC-1:0] calibrate_a_dec;
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always @(posedge clk) begin
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calibrate_a_dec <= 0;
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calibrate_a_dec[calibrate_a_r] <= !flush;
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end
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wire [CHAIN_LEN:0] chain_a = {CHAIN_LEN{1'b1}} + calibrate_a_dec;
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wire a_out = chain_a[CHAIN_LEN];
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///////////////////////
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// path B
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///////////////////////
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reg [CALIBRATE_DEC-1:0] calibrate_b_dec;
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always @(posedge clk) begin
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calibrate_b_dec <= 0;
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calibrate_b_dec[calibrate_b_r] <= !flush;
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end
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wire [CHAIN_LEN:0] chain_b = {CHAIN_LEN{1'b1}} + calibrate_b_dec;
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wire b_out = chain_b[CHAIN_LEN];
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///////////////////////
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// finish line latches
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///////////////////////
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wire a_wins_latch, b_wins_latch /* synthesis keep */;
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wire trial_complete = a_out & b_out;
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assign a_wins_latch = !flush & (a_wins_latch | (a_out & !b_out));
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assign b_wins_latch = !flush & (b_wins_latch | (b_out & !a_out));
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///////////////////////
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// resynchronize
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///////////////////////
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reg a_wins, b_wins, stable /* synthesis preserve */;
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always @(posedge clk) begin
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a_wins <= a_wins_latch;
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b_wins <= b_wins_latch;
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stable <= trial_complete;
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end
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////////////////////////////////////
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// control - continuous retrigger
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////////////////////////////////////
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reg [1:0] state /* synthesis preserve */;
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always @(posedge clk) begin
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if (rst) begin
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flush <= 1'b1;
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state <= 2'b00;
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valid <= 1'b0;
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end
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else begin
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case (state)
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2'b00 : begin
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flush <= 1'b1;
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valid <= 1'b0;
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if (!a_wins & !b_wins & !stable) state <= 2'b01;
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end
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2'b01 : begin
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flush <= 1'b0;
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if (stable) state <= 2'b10;
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end
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2'b10 : begin
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valid <= 1'b1;
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state <= 2'b00;
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end
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2'b11 : begin
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// unreachable
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state <= 2'b00;
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end
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endcase
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end
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end
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endmodule |