mirror of
https://github.com/pConst/basic_verilog.git
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105 lines
2.9 KiB
Tcl
105 lines
2.9 KiB
Tcl
#------------------------------------------------------------------------------
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# compile.tcl
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# Modelsim compile script
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# based on "ModelSimSE general compile script version 1.1" by Doulos
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# launch the script by "vsim -do compile.tcl" command on linux
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# or by "modelsim.exe -do compile.tcl" on windows
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# Simply change the project settings in this section
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# for each new project. There should be no need to
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# modify the rest of the script.
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set library_file_list {
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work {fifo_tb.sv
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fifo.sv
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test.vo
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c_rand.v
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edge_detect.sv
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clk_divider.sv}
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}
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../../c_rand.v
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../../edge_detect.sv
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../../delay.sv
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../../clk_divider.sv}
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}
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set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
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# add these parameters when simulating Quartus netlists
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# "+transport_int_delays +transport_path_delays -L altera_ver -L altera_lnsim_ver -L cyclonev_ver -L lpm_ver -L sgate_ver -L cyclonev_hssi_ver -L altera_mf_ver -L cyclonev_pcie_hip_ver"
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set top_level work.fifo_tb
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# Console commands:
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# r = Recompile changed and dependent files
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# rr = Recompile everything
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# q = Quit without confirmation
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# After sourcing the script from ModelSim for the
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# first time use these commands to recompile.
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proc r {} {uplevel #0 source compile.tcl}
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proc rr {} {global last_compile_time
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set last_compile_time 0
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r }
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proc q {} {quit -force }
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#Does this installation support Tk?
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set tk_ok 1
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if [catch {package require Tk}] {set tk_ok 0}
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# Prefer a fixed point font for the transcript
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set PrefMain(font) {Courier 10 roman normal}
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# Compile out of date files
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set time_now [clock seconds]
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if [catch {set last_compile_time}] {
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set last_compile_time 0
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}
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foreach {library file_list} $library_file_list {
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vlib $library
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vmap work $library
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foreach file $file_list {
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if { $last_compile_time < [file mtime $file] } {
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if [regexp {.vhdl?$} $file] {
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vcom -93 $file
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} else {
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vlog $file
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}
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set last_compile_time 0
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}
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}
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}
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set last_compile_time $time_now
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# Load the simulation
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eval vsim $top_level $vsim_params
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# Load saved wave patterns
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do wave.do
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# Run the simulation
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run 100us
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wave zoom range 0 100us
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# How long since project began?
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if {[file isfile start_time.txt] == 0} {
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set f [open start_time.txt w]
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puts $f "Start time was [clock seconds]"
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close $f
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} else {
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set f [open start_time.txt r]
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set line [gets $f]
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close $f
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regexp {\d+} $line start_time
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set total_time [expr ([clock seconds]-$start_time)/60]
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puts "Project time is $total_time minutes"
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}
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