mirror of
https://github.com/pConst/basic_verilog.git
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212 lines
7.5 KiB
Verilog
212 lines
7.5 KiB
Verilog
/*
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This file is a simple top level that will generate one of four types of
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Avalon-MM master. As a result all the ports must be declared and it will be
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up to the component .tcl file to stub unused signals.
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*/
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// altera message_off 10034
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module custom_master (
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clk,
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reset,
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// control inputs and outputs
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control_fixed_location,
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control_read_base,
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control_read_length,
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control_write_base,
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control_write_length,
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control_go,
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control_done,
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control_early_done,
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// user logic inputs and outputs
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user_read_buffer,
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user_write_buffer,
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user_buffer_input_data,
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user_buffer_output_data,
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user_data_available,
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user_buffer_full,
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// master inputs and outputs
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master_address,
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master_read,
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master_write,
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master_byteenable,
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master_readdata,
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master_readdatavalid,
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master_writedata,
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master_burstcount,
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master_waitrequest
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);
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parameter MASTER_DIRECTION = 0; // 0 for read master, 1 for write master
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parameter DATA_WIDTH = 32;
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parameter MEMORY_BASED_FIFO = 1; // 0 for LE/ALUT FIFOs, 1 for memory FIFOs (highly recommend 1)
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parameter FIFO_DEPTH = 32;
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parameter FIFO_DEPTH_LOG2 = 5;
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parameter ADDRESS_WIDTH = 32;
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parameter BURST_CAPABLE = 0; // 1 to enable burst, 0 to disable it
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parameter MAXIMUM_BURST_COUNT = 2;
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parameter BURST_COUNT_WIDTH = 2;
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input clk;
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input reset;
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// control inputs and outputs
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input control_fixed_location;
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input [ADDRESS_WIDTH-1:0] control_read_base; // for read master
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input [ADDRESS_WIDTH-1:0] control_read_length; // for read master
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input [ADDRESS_WIDTH-1:0] control_write_base; // for write master
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input [ADDRESS_WIDTH-1:0] control_write_length; // for write master
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input control_go;
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output wire control_done;
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output wire control_early_done; // for read master
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// user logic inputs and outputs
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input user_read_buffer; // for read master
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input user_write_buffer; // for write master
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input [DATA_WIDTH-1:0] user_buffer_input_data; // for write master
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output wire [DATA_WIDTH-1:0] user_buffer_output_data; // for read master
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output wire user_data_available; // for read master
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output wire user_buffer_full; // for write master
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// master inputs and outputs
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output wire [ADDRESS_WIDTH-1:0] master_address;
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output wire master_read; // for read master
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output wire master_write; // for write master
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output wire [(DATA_WIDTH/8)-1:0] master_byteenable;
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input [DATA_WIDTH-1:0] master_readdata; // for read master
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input master_readdatavalid; // for read master
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output wire [DATA_WIDTH-1:0] master_writedata; // for write master
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output wire [BURST_COUNT_WIDTH-1:0] master_burstcount; // for bursting read and write masters
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input master_waitrequest;
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generate // big generate if statement to select the approprate master depending on the direction and burst parameters
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if(MASTER_DIRECTION == 0)
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begin
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if(BURST_CAPABLE == 1)
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begin
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burst_read_master a_burst_read_master(
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.clk (clk),
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.reset (reset),
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.control_fixed_location (control_fixed_location),
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.control_read_base (control_read_base),
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.control_read_length (control_read_length),
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.control_go (control_go),
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.control_done (control_done),
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.control_early_done (control_early_done),
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.user_read_buffer (user_read_buffer),
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.user_buffer_data (user_buffer_output_data),
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.user_data_available (user_data_available),
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.master_address (master_address),
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.master_read (master_read),
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.master_byteenable (master_byteenable),
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.master_readdata (master_readdata),
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.master_readdatavalid (master_readdatavalid),
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.master_burstcount (master_burstcount),
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.master_waitrequest (master_waitrequest)
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);
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defparam a_burst_read_master.DATAWIDTH = DATA_WIDTH;
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defparam a_burst_read_master.MAXBURSTCOUNT = MAXIMUM_BURST_COUNT;
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defparam a_burst_read_master.BURSTCOUNTWIDTH = BURST_COUNT_WIDTH;
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defparam a_burst_read_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
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defparam a_burst_read_master.ADDRESSWIDTH = ADDRESS_WIDTH;
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defparam a_burst_read_master.FIFODEPTH = FIFO_DEPTH;
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defparam a_burst_read_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
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defparam a_burst_read_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
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end
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else
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begin
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latency_aware_read_master a_latency_aware_read_master(
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.clk (clk),
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.reset (reset),
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.control_fixed_location (control_fixed_location),
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.control_read_base (control_read_base),
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.control_read_length (control_read_length),
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.control_go (control_go),
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.control_done (control_done),
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.control_early_done (control_early_done),
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.user_read_buffer (user_read_buffer),
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.user_buffer_data (user_buffer_output_data),
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.user_data_available (user_data_available),
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.master_address (master_address),
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.master_read (master_read),
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.master_byteenable (master_byteenable),
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.master_readdata (master_readdata),
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.master_readdatavalid (master_readdatavalid),
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.master_waitrequest (master_waitrequest)
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);
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defparam a_latency_aware_read_master.DATAWIDTH = DATA_WIDTH;
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defparam a_latency_aware_read_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
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defparam a_latency_aware_read_master.ADDRESSWIDTH = ADDRESS_WIDTH;
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defparam a_latency_aware_read_master.FIFODEPTH = FIFO_DEPTH;
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defparam a_latency_aware_read_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
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defparam a_latency_aware_read_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
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end
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end
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else
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begin
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if(BURST_CAPABLE == 1)
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begin
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burst_write_master a_burst_write_master(
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.clk (clk),
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.reset (reset),
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.control_fixed_location (control_fixed_location),
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.control_write_base (control_write_base),
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.control_write_length (control_write_length),
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.control_go (control_go),
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.control_done (control_done),
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.user_write_buffer (user_write_buffer),
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.user_buffer_data (user_buffer_input_data),
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.user_buffer_full (user_buffer_full),
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.master_address (master_address),
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.master_write (master_write),
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.master_byteenable (master_byteenable),
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.master_writedata (master_writedata),
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.master_burstcount (master_burstcount),
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.master_waitrequest (master_waitrequest)
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);
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defparam a_burst_write_master.DATAWIDTH = DATA_WIDTH;
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defparam a_burst_write_master.MAXBURSTCOUNT = MAXIMUM_BURST_COUNT;
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defparam a_burst_write_master.BURSTCOUNTWIDTH = BURST_COUNT_WIDTH;
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defparam a_burst_write_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
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defparam a_burst_write_master.ADDRESSWIDTH = ADDRESS_WIDTH;
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defparam a_burst_write_master.FIFODEPTH = FIFO_DEPTH;
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defparam a_burst_write_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
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defparam a_burst_write_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
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end
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else
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begin
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write_master a_write_master(
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.clk (clk),
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.reset (reset),
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.control_fixed_location (control_fixed_location),
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.control_write_base (control_write_base),
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.control_write_length (control_write_length),
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.control_go (control_go),
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.control_done (control_done),
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.user_write_buffer (user_write_buffer),
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.user_buffer_data (user_buffer_input_data),
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.user_buffer_full (user_buffer_full),
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.master_address (master_address),
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.master_write (master_write),
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.master_byteenable (master_byteenable),
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.master_writedata (master_writedata),
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.master_waitrequest (master_waitrequest)
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);
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defparam a_write_master.DATAWIDTH = DATA_WIDTH;
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defparam a_write_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
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defparam a_write_master.ADDRESSWIDTH = ADDRESS_WIDTH;
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defparam a_write_master.FIFODEPTH = FIFO_DEPTH;
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defparam a_write_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
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defparam a_write_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
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end
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end
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endgenerate
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endmodule
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