mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-28 07:02:55 +08:00
80 lines
2.3 KiB
JSON
80 lines
2.3 KiB
JSON
{
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"Allow_Duplicate_Modules" : false,
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"Annotated_Properties_for_Analyst" : true,
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"BACKGROUND_PROGRAMMING" : "off",
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"COMPRESS" : false,
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"CRC_CHECK" : true,
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"Clock_Conversion" : true,
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"DONE" : false,
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"DOWNLOAD_SPEED" : "default",
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"Default_Enum_Encoding" : "default",
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"Disable_Insert_Pad" : false,
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"ENCRYPTION_KEY" : false,
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"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
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"FORMAT" : "binary",
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"FSM Compiler" : true,
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"Fanout_Guide" : 10000,
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"Frequency" : "Auto",
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"Generate_Constraint_File_of_Ports" : false,
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"Generate_IBIS_File" : false,
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"Generate_Plain_Text_Timing_Report" : false,
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"Generate_Post_PNR_Simulation_Model_File" : false,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"GwSyn_Loop_Limit" : 2000,
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"HOTBOOT" : false,
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"I2C" : false,
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"I2C_SLAVE_ADDR" : "00",
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"Implicit_Initial_Value_Support" : false,
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"IncludePath" : [
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],
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"Incremental_Compile" : "",
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"MSPI" : false,
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"Multiple_File_Compilation_Unit" : true,
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"Number_of_Critical_Paths" : "",
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"Number_of_Start/End_Points" : "",
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"OUTPUT_BASE_NAME" : "gowin_benchmark",
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"POWER_ON_RESET" : false,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,
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"Pipelining" : true,
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"PlaceInRegToIob" : true,
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"PlaceIoRegToIob" : true,
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"PlaceOutRegToIob" : true,
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"Place_Option" : "0",
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : false,
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"Push_Tristates" : true,
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"READY" : false,
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"RECONFIG_N" : false,
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"Ram_RW_Check" : true,
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"Report_Auto-Placed_Io_Information" : false,
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"Resolve_Mixed_Drivers" : false,
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"Resource_Sharing" : true,
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"Retiming" : false,
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"Route_Option" : "0",
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"Run_Timing_Driven" : true,
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"SECURE_MODE" : false,
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"SECURITY_BIT" : true,
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"SPI_FLASH_ADDR" : "00000000",
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"SSPI" : false,
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"Show_All_Warnings" : false,
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"Synthesis On/Off Implemented as Translate On/Off" : false,
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"Synthesize_tool" : "GowinSyn",
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"TopModule" : "main",
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"USERCODE" : "default",
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"Unused_Pin" : "As_input_tri_stated_with_pull_up",
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"Update_Compile_Point_Timing_Data" : false,
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"Use_Clock_Period_for_Unconstrainted IO" : false,
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"Use_SCF" : false,
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"VHDL_Standard" : "VHDL_Std_1993",
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"Verilog_Standard" : "Vlg_Std_Sysv2017",
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"WAKE_UP" : "0",
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"Write_Vendor_Constraint_File" : true,
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"dsp_balance" : false,
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"show_all_warnings" : false
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} |