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82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 05-05-2006
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// testbench for min_max
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////////////////////////////////////////////
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module min_max_tb ();
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parameter WIDTH = 8;
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reg clk,rst,sign;
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reg [WIDTH-1:0] a,b;
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wire [WIDTH-1:0] min_ab,max_ab;
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wire [WIDTH-1:0] min_abu,max_abu;
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wire [WIDTH-1:0] min_ab8,max_ab8;
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min_max_signed mm (.clk(clk),.rst(rst),.a(a),.b(b),
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.min_ab(min_ab),.max_ab(max_ab));
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defparam mm .WIDTH = WIDTH;
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min_max_unsigned mmu (.clk(clk),.rst(rst),.a(a),.b(b),
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.min_ab(min_abu),.max_ab(max_abu));
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defparam mmu .WIDTH = WIDTH;
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min_max_8bit m8 (.clk(clk),.rst(rst),.a_in(a),.b_in(b),
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.is_signed(sign),
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.min_ab(min_ab8),.max_ab(max_ab8));
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reg fail = 0;
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initial begin
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clk = 0;
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rst = 0;
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sign = 0;
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#10 rst = 1;
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#10 rst = 0;
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#1000000 if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clk = ~clk;
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end
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always @(negedge clk) begin
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a = $random;
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b = $random;
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sign = $random;
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end
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always @(posedge clk) begin
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#10 if (sign & (min_ab8 != min_ab || min_ab8 != min_ab) |
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!sign & (min_ab8 != min_abu || min_ab8 != min_abu))
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begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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endmodule
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