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109 lines
3.1 KiB
Verilog
109 lines
3.1 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 09-15-2008
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//
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// Sum of two 3-bit numbers, targeting exactly four LUTs
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// {6,6,4,2} inputs
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//
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module sum_of_3bit_pair
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(
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input [2:0] a,b,
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output reg [3:0] sum
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);
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always @(*) begin
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case ({a,b})
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6'd0: sum=4'd0;
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6'd1: sum=4'd1;
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6'd2: sum=4'd2;
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6'd3: sum=4'd3;
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6'd4: sum=4'd4;
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6'd5: sum=4'd5;
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6'd6: sum=4'd6;
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6'd7: sum=4'd7;
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6'd8: sum=4'd1;
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6'd9: sum=4'd2;
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6'd10: sum=4'd3;
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6'd11: sum=4'd4;
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6'd12: sum=4'd5;
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6'd13: sum=4'd6;
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6'd14: sum=4'd7;
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6'd15: sum=4'd8;
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6'd16: sum=4'd2;
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6'd17: sum=4'd3;
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6'd18: sum=4'd4;
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6'd19: sum=4'd5;
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6'd20: sum=4'd6;
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6'd21: sum=4'd7;
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6'd22: sum=4'd8;
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6'd23: sum=4'd9;
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6'd24: sum=4'd3;
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6'd25: sum=4'd4;
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6'd26: sum=4'd5;
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6'd27: sum=4'd6;
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6'd28: sum=4'd7;
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6'd29: sum=4'd8;
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6'd30: sum=4'd9;
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6'd31: sum=4'd10;
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6'd32: sum=4'd4;
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6'd33: sum=4'd5;
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6'd34: sum=4'd6;
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6'd35: sum=4'd7;
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6'd36: sum=4'd8;
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6'd37: sum=4'd9;
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6'd38: sum=4'd10;
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6'd39: sum=4'd11;
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6'd40: sum=4'd5;
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6'd41: sum=4'd6;
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6'd42: sum=4'd7;
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6'd43: sum=4'd8;
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6'd44: sum=4'd9;
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6'd45: sum=4'd10;
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6'd46: sum=4'd11;
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6'd47: sum=4'd12;
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6'd48: sum=4'd6;
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6'd49: sum=4'd7;
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6'd50: sum=4'd8;
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6'd51: sum=4'd9;
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6'd52: sum=4'd10;
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6'd53: sum=4'd11;
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6'd54: sum=4'd12;
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6'd55: sum=4'd13;
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6'd56: sum=4'd7;
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6'd57: sum=4'd8;
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6'd58: sum=4'd9;
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6'd59: sum=4'd10;
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6'd60: sum=4'd11;
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6'd61: sum=4'd12;
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6'd62: sum=4'd13;
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6'd63: sum=4'd14;
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default: sum=0;
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endcase
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end
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endmodule
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