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139 lines
3.4 KiB
Verilog
139 lines
3.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-24-2007
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module simple_quad_tb ();
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parameter ADDR_WIDTH = 5;
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parameter NUM_WORDS = 1 << ADDR_WIDTH;
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parameter DATA_WIDTH = 32;
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reg clk;
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reg [ADDR_WIDTH-1:0] wraddr_a,wraddr_b,rdaddr_a,rdaddr_b;
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reg [DATA_WIDTH-1:0] wrdat_a,wrdat_b;
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reg we_a,we_b;
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wire [DATA_WIDTH-1:0] rddat_a,rddat_b;
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reg fail = 1'b0;
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////////////////
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// DUT
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////////////////
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simple_quad sq (
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.clk(clk),
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.wraddr_a(wraddr_a),
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.wraddr_b(wraddr_b),
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.wrdat_a(wrdat_a),
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.wrdat_b(wrdat_b),
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.we_a(we_a),
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.we_b(we_b),
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.rdaddr_a(rdaddr_a),
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.rdaddr_b(rdaddr_b),
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.rddat_a(rddat_a),
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.rddat_b(rddat_b)
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);
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defparam sq .ADDR_WIDTH = ADDR_WIDTH;
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defparam sq .DATA_WIDTH = DATA_WIDTH;
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////////////////////
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// Functional Model
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////////////////////
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reg [DATA_WIDTH-1:0] store [0:NUM_WORDS-1];
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reg [NUM_WORDS-1:0] valid;
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reg valid_rda, valid_rdb;
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reg [ADDR_WIDTH-1:0] waar,wabr,raar,rabr;
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reg [DATA_WIDTH-1:0] wdar,wdbr,rda,rdb;
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reg wear,webr;
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initial valid = 0;
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always @(posedge clk) begin
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waar <= wraddr_a;
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wabr <= wraddr_b;
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wdar <= wrdat_a;
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wdbr <= wrdat_b;
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wear <= we_a;
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webr <= we_b;
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if (wear) begin
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store[waar] <= wdar;
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valid[waar] <= 1'b1;
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end
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if (webr) begin
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store[wabr] <= wdbr;
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valid[wabr] <= 1'b1;
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end
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raar <= rdaddr_a;
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rabr <= rdaddr_b;
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rda <= store[raar];
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rdb <= store[rabr];
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valid_rda <= valid[raar];
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valid_rdb <= valid[rabr];
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end
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always @(posedge clk) begin
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#10 if (valid_rda && (rda !== rddat_a)) begin
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$display ("Mismatch on port A");
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fail = 1'b1;
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end
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if (valid_rdb && (rdb !== rddat_b)) begin
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$display ("Mismatch on port B");
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fail = 1'b1;
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end
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end
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////////////////////
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// Test driver
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////////////////////
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initial begin
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clk = 0;
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rdaddr_a = 5'h0;
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rdaddr_b = 5'h0;
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#100000000 if (!fail) $display ("PASS");
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$stop();
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end
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reg [23:0] tmp_a,tmp_b;
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always @(negedge clk) begin
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rdaddr_a = $random;
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rdaddr_b = $random;
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wraddr_a = $random;
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wraddr_b = $random;
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tmp_a = $random;
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tmp_b = $random;
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wrdat_a = {2'b0,wraddr_a,tmp_a};
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wrdat_b = {2'b0,wraddr_b,tmp_b};
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we_a = 1'b1;
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we_b = 1'b1;
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end
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always begin
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#100 clk = ~clk;
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end
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endmodule |