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82 lines
2.8 KiB
Verilog
82 lines
2.8 KiB
Verilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 12-14-2009
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module gearbox_20_22 (
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input clk,
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input odd, // select a shift by 1 bit of the data
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input drop2, // slip to lose 2 bits of data
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input [19:0] din, // lsbit used first
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output reg [21:0] dout,
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output reg dout_valid
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);
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reg [19:0] din_r = 20'h0;
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reg extra_din_r = 1'b0;
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always @(posedge clk) begin
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if (odd) begin
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{extra_din_r,din_r} <= {din,extra_din_r};
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end
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else begin
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din_r <= din;
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end
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end
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reg [3:0] gbstate = 4'b0 /* synthesis preserve */;
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always @(posedge clk) begin
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if (gbstate == 4'ha) gbstate <= 4'h0;
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else gbstate <= gbstate + (drop2 ? 2'd2 : 2'd1);
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end
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reg [20 + 20 - 1:0] storage = 39'b0;
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reg dout_valid_i = 1'b0;
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always @(posedge clk) begin
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case (gbstate)
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4'h0: storage <= {20'b0,din_r};
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4'h1: storage <= {din_r,storage[19:0]};
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4'h2: storage <= {2'b0,din_r,storage[39:22]};
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4'h3: storage <= {4'b0,din_r,storage[37:22]};
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4'h4: storage <= {6'b0,din_r,storage[35:22]};
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4'h5: storage <= {8'b0,din_r,storage[33:22]};
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4'h6: storage <= {10'b0,din_r,storage[31:22]};
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4'h7: storage <= {12'b0,din_r,storage[29:22]};
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4'h8: storage <= {14'b0,din_r,storage[27:22]};
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4'h9: storage <= {16'b0,din_r,storage[25:22]};
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4'ha: storage <= {18'b0,din_r,storage[23:22]};
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default: storage <= {20'b0,din_r};
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endcase
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dout_valid_i <= |gbstate;
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end
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initial dout = 22'b0;
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initial dout_valid = 1'b0;
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always @(posedge clk) begin
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dout_valid <= dout_valid_i;
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dout <= storage [21:0];
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end
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endmodule |