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86 lines
2.4 KiB
Verilog
86 lines
2.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-16-2007
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module uart_hw_test (clk,rst_n,txd,rxd);
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input clk,rst_n;
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input rxd;
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output txd;
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reg [7:0] tx_data;
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reg tx_data_valid;
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wire tx_data_ack;
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wire txd,rxd;
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wire [7:0] rx_data;
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wire rx_data_fresh;
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reg [7:0] rst_cntr;
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reg rst;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rst_cntr <= 0;
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rst <= 1'b1;
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end
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else begin
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if (&rst_cntr) begin
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rst <= 1'b0;
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end
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else begin
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rst <= 1'b1;
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rst_cntr <= rst_cntr + 1'b1;
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end
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end
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end
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uart u (.clk(clk),
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.rst(rst),
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.tx_data(tx_data),
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.tx_data_valid(tx_data_valid),
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.tx_data_ack(tx_data_ack),
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.txd(txd),
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.rx_data(rx_data),
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.rx_data_fresh(rx_data_fresh),
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.rxd(rxd));
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defparam u .CLK_HZ = 100_000_000;
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defparam u .BAUD = 115200;
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// add one to each RX byte and send it out again
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always @(posedge clk) begin
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if (rst) begin
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tx_data <= 1'b0;
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tx_data_valid <= 1'b0;
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end
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else begin
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if (rx_data_fresh) begin
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tx_data <= rx_data + 1'b1;
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tx_data_valid <= 1'b1;
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end
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else if (tx_data_ack) begin
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tx_data_valid <= 1'b0;
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end
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end
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end
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endmodule
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