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81 lines
2.2 KiB
Systemverilog
81 lines
2.2 KiB
Systemverilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module ready_skid_tb ();
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parameter WIDTH = 12;
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reg clk,arst;
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reg valid_i;
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reg [WIDTH-1:0] dat_i, last_o;
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wire ready_i;
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wire valid_o;
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wire [WIDTH-1:0] dat_o;
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reg ready_o;
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ready_skid #(.WIDTH(WIDTH)) dut
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(
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.*
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);
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initial begin
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clk = 0;
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dat_i = 0;
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valid_i = 0;
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ready_o = 0;
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last_o = 0;
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arst = 0;
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#1 arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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end
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always begin
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#5 clk = ~clk;
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end
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always @(negedge clk) begin
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valid_i = $random | $random;
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if (valid_i & ready_i) dat_i = dat_i + 1'b1;
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ready_o = $random | $random;
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end
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reg fail = 0;
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wire [WIDTH-1:0] next_last_o = last_o + 1'b1;
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always @(posedge clk) begin
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if (valid_o) last_o <= dat_o;
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#1 if (last_o != dat_o && next_last_o != dat_o) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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initial begin
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#1000000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule
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