This website requires JavaScript.
Explore
Help
Sign In
FPGA
/
basic_verilog
Watch
1
Star
0
Fork
0
You've already forked basic_verilog
mirror of
https://github.com/pConst/basic_verilog.git
synced
2025-01-14 06:42:54 +08:00
Code
Issues
Releases
Wiki
Activity
basic_verilog
/
gitignores
History
Konstantin Pavlov
553e74c437
Updated Vivado gitignore
2022-11-11 14:29:24 +03:00
..
.gitignore_gowin
Added gitignore and clen script for Gowin IDE projects
2022-05-16 18:58:36 +03:00
.gitignore_modelsim
Update Modelsim gitignore
2022-07-03 16:38:37 +03:00
.gitignore_quartus
Added gitignore and clen script for Gowin IDE projects
2022-05-16 18:58:36 +03:00
.gitignore_vivado
Updated Vivado gitignore
2022-11-11 14:29:24 +03:00