mirror of
https://github.com/pConst/basic_verilog.git
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616 lines
22 KiB
Verilog
Executable File
616 lines
22 KiB
Verilog
Executable File
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`timescale 1 ns / 1 ps
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module S00_axi_lite #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Width of ID for for write address, write data, read address and read data
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parameter integer C_S_AXI_ID_WIDTH = 1,
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// Width of S_AXI data bus
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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// Width of S_AXI address bus
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parameter integer C_S_AXI_ADDR_WIDTH = 6,
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// Width of optional user defined signal in write address channel
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parameter integer C_S_AXI_AWUSER_WIDTH = 0,
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// Width of optional user defined signal in read address channel
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parameter integer C_S_AXI_ARUSER_WIDTH = 0,
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// Width of optional user defined signal in write data channel
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parameter integer C_S_AXI_WUSER_WIDTH = 0,
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// Width of optional user defined signal in read data channel
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parameter integer C_S_AXI_RUSER_WIDTH = 0,
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// Width of optional user defined signal in write response channel
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parameter integer C_S_AXI_BUSER_WIDTH = 0
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)
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(
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// Users to add ports here
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// User ports ends
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// Do not modify the ports beyond this line
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// Global Clock Signal
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input wire S_AXI_ACLK,
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// Global Reset Signal. This Signal is Active LOW
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input wire S_AXI_ARESETN,
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// Write Address ID
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input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
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// Write address
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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input wire [7 : 0] S_AXI_AWLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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input wire [2 : 0] S_AXI_AWSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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input wire [1 : 0] S_AXI_AWBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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input wire S_AXI_AWLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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input wire [3 : 0] S_AXI_AWCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_AWPROT,
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// Quality of Service, QoS identifier sent for each
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// write transaction.
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input wire [3 : 0] S_AXI_AWQOS,
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// Region identifier. Permits a single physical interface
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// on a slave to be used for multiple logical interfaces.
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input wire [3 : 0] S_AXI_AWREGION,
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// Optional User-defined signal in the write address channel.
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input wire [C_S_AXI_AWUSER_WIDTH-1 : 0] S_AXI_AWUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid write address and
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// control information.
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input wire S_AXI_AWVALID,
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// Write address ready. This signal indicates that
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// the slave is ready to accept an address and associated
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// control signals.
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output wire S_AXI_AWREADY,
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// Write Data
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
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// Write strobes. This signal indicates which byte
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// lanes hold valid data. There is one write strobe
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// bit for each eight bits of the write data bus.
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
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// Write last. This signal indicates the last transfer
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// in a write burst.
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input wire S_AXI_WLAST,
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// Optional User-defined signal in the write data channel.
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input wire [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER,
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// Write valid. This signal indicates that valid write
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// data and strobes are available.
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input wire S_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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output wire S_AXI_WREADY,
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// Response ID tag. This signal is the ID tag of the
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// write response.
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output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
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// Write response. This signal indicates the status
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// of the write transaction.
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output wire [1 : 0] S_AXI_BRESP,
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// Optional User-defined signal in the write response channel.
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output wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER,
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// Write response valid. This signal indicates that the
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// channel is signaling a valid write response.
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output wire S_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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input wire S_AXI_BREADY,
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// Read address ID. This signal is the identification
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// tag for the read address group of signals.
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input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
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// Read address. This signal indicates the initial
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// address of a read burst transaction.
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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input wire [7 : 0] S_AXI_ARLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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input wire [2 : 0] S_AXI_ARSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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input wire [1 : 0] S_AXI_ARBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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input wire S_AXI_ARLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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input wire [3 : 0] S_AXI_ARCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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input wire [2 : 0] S_AXI_ARPROT,
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// Quality of Service, QoS identifier sent for each
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// read transaction.
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input wire [3 : 0] S_AXI_ARQOS,
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// Region identifier. Permits a single physical interface
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// on a slave to be used for multiple logical interfaces.
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input wire [3 : 0] S_AXI_ARREGION,
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// Optional User-defined signal in the read address channel.
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input wire [C_S_AXI_ARUSER_WIDTH-1 : 0] S_AXI_ARUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid read address and
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// control information.
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input wire S_AXI_ARVALID,
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// Read address ready. This signal indicates that
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// the slave is ready to accept an address and associated
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// control signals.
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output wire S_AXI_ARREADY,
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// Read ID tag. This signal is the identification tag
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// for the read data group of signals generated by the slave.
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output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
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// Read Data
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
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// Read response. This signal indicates the status of
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// the read transfer.
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output wire [1 : 0] S_AXI_RRESP,
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// Read last. This signal indicates the last transfer
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// in a read burst.
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output wire S_AXI_RLAST,
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// Optional User-defined signal in the read address channel.
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output wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER,
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// Read valid. This signal indicates that the channel
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// is signaling the required read data.
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output wire S_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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input wire S_AXI_RREADY
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);
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// AXI4FULL signals
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg axi_awready;
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reg axi_wready;
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reg [1 : 0] axi_bresp;
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reg [C_S_AXI_BUSER_WIDTH-1 : 0] axi_buser;
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reg axi_bvalid;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg axi_arready;
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reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
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reg [1 : 0] axi_rresp;
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reg axi_rlast;
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reg [C_S_AXI_RUSER_WIDTH-1 : 0] axi_ruser;
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reg axi_rvalid;
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// aw_wrap_en determines wrap boundary and enables wrapping
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wire aw_wrap_en;
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// ar_wrap_en determines wrap boundary and enables wrapping
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wire ar_wrap_en;
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// aw_wrap_size is the size of the write transfer, the
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// write address wraps to a lower address if upper address
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// limit is reached
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wire [31:0] aw_wrap_size ;
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// ar_wrap_size is the size of the read transfer, the
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// read address wraps to a lower address if upper address
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// limit is reached
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wire [31:0] ar_wrap_size ;
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// The axi_awv_awr_flag flag marks the presence of write address valid
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reg axi_awv_awr_flag;
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//The axi_arv_arr_flag flag marks the presence of read address valid
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reg axi_arv_arr_flag;
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// The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
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reg [7:0] axi_awlen_cntr;
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//The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
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reg [7:0] axi_arlen_cntr;
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reg [1:0] axi_arburst;
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reg [1:0] axi_awburst;
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reg [7:0] axi_arlen;
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reg [7:0] axi_awlen;
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//local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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//ADDR_LSB is used for addressing 32/64 bit registers/memories
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//ADDR_LSB = 2 for 32 bits (n downto 2)
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//ADDR_LSB = 3 for 42 bits (n downto 3)
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localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
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localparam integer OPT_MEM_ADDR_BITS = 3;
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localparam integer USER_NUM_MEM = 1;
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//----------------------------------------------
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//-- Signals for user logic memory space example
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//------------------------------------------------
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wire [OPT_MEM_ADDR_BITS:0] mem_address;
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wire [USER_NUM_MEM-1:0] mem_select;
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reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
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genvar i;
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genvar j;
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genvar mem_byte_index;
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// I/O Connections assignments
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_WREADY = axi_wready;
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assign S_AXI_BRESP = axi_bresp;
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assign S_AXI_BUSER = axi_buser;
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assign S_AXI_BVALID = axi_bvalid;
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assign S_AXI_ARREADY = axi_arready;
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assign S_AXI_RDATA = axi_rdata;
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assign S_AXI_RRESP = axi_rresp;
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assign S_AXI_RLAST = axi_rlast;
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assign S_AXI_RUSER = axi_ruser;
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assign S_AXI_RVALID = axi_rvalid;
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assign S_AXI_BID = S_AXI_AWID;
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assign S_AXI_RID = S_AXI_ARID;
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assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen));
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assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen));
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assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
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assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
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// Implement axi_awready generation
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// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_awready <= 1'b0;
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axi_awv_awr_flag <= 1'b0;
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end
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else
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begin
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if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
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begin
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// slave is ready to accept an address and
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// associated control signals
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axi_awready <= 1'b1;
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axi_awv_awr_flag <= 1'b1;
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// used for generation of bresp() and bvalid
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end
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else if (S_AXI_WLAST && axi_wready)
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// preparing to accept next address after current write burst tx completion
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begin
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axi_awv_awr_flag <= 1'b0;
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end
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else
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begin
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axi_awready <= 1'b0;
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end
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end
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end
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// Implement axi_awaddr latching
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// This process is used to latch the address when both
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// S_AXI_AWVALID and S_AXI_WVALID are valid.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_awaddr <= 0;
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axi_awlen_cntr <= 0;
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axi_awburst <= 0;
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axi_awlen <= 0;
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end
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else
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begin
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if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
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begin
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// address latching
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axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];
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axi_awburst <= S_AXI_AWBURST;
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axi_awlen <= S_AXI_AWLEN;
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// start address of transfer
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axi_awlen_cntr <= 0;
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end
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else if((axi_awlen_cntr <= axi_awlen) && axi_wready && S_AXI_WVALID)
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begin
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axi_awlen_cntr <= axi_awlen_cntr + 1;
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case (axi_awburst)
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2'b00: // fixed burst
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// The write address for all the beats in the transaction are fixed
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begin
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axi_awaddr <= axi_awaddr;
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//for awsize = 4 bytes (010)
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end
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2'b01: //incremental burst
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// The write address for all the beats in the transaction are increments by awsize
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begin
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axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
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//awaddr aligned to 4 byte boundary
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axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
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//for awsize = 4 bytes (010)
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end
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2'b10: //Wrapping burst
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// The write address wraps when the address reaches wrap boundary
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if (aw_wrap_en)
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begin
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axi_awaddr <= (axi_awaddr - aw_wrap_size);
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end
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else
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begin
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axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
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axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
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end
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default: //reserved (incremental burst for example)
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begin
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axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
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//for awsize = 4 bytes (010)
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end
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endcase
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end
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end
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end
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// Implement axi_wready generation
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// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
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// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
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// de-asserted when reset is low.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_wready <= 1'b0;
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end
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else
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begin
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if ( ~axi_wready && S_AXI_WVALID && axi_awv_awr_flag)
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begin
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// slave can accept the write data
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axi_wready <= 1'b1;
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end
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//else if (~axi_awv_awr_flag)
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else if (S_AXI_WLAST && axi_wready)
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begin
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axi_wready <= 1'b0;
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end
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end
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end
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// Implement write response logic generation
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// The write response and response valid signals are asserted by the slave
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// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
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// This marks the acceptance of address and indicates the status of
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// write transaction.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_bvalid <= 0;
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axi_bresp <= 2'b0;
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axi_buser <= 0;
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end
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else
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begin
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if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid && S_AXI_WLAST )
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begin
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axi_bvalid <= 1'b1;
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axi_bresp <= 2'b0;
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// 'OKAY' response
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end
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else
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begin
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if (S_AXI_BREADY && axi_bvalid)
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//check if bready is asserted while bvalid is high)
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//(there is a possibility that bready is always asserted high)
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begin
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axi_bvalid <= 1'b0;
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end
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end
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end
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end
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// Implement axi_arready generation
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// axi_arready is asserted for one S_AXI_ACLK clock cycle when
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// S_AXI_ARVALID is asserted. axi_awready is
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// de-asserted when reset (active low) is asserted.
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// The read address is also latched when S_AXI_ARVALID is
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// asserted. axi_araddr is reset to zero on reset assertion.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_arready <= 1'b0;
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axi_arv_arr_flag <= 1'b0;
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end
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else
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begin
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if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
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begin
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axi_arready <= 1'b1;
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axi_arv_arr_flag <= 1'b1;
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end
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else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == axi_arlen)
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// preparing to accept next address after current read completion
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begin
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axi_arv_arr_flag <= 1'b0;
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end
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else
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begin
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axi_arready <= 1'b0;
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end
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end
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end
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// Implement axi_araddr latching
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//This process is used to latch the address when both
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//S_AXI_ARVALID and S_AXI_RVALID are valid.
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always @( posedge S_AXI_ACLK )
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begin
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if ( S_AXI_ARESETN == 1'b0 )
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begin
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axi_araddr <= 0;
|
|
axi_arlen_cntr <= 0;
|
|
axi_arburst <= 0;
|
|
axi_arlen <= 0;
|
|
axi_rlast <= 1'b0;
|
|
axi_ruser <= 0;
|
|
end
|
|
else
|
|
begin
|
|
if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
|
|
begin
|
|
// address latching
|
|
axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0];
|
|
axi_arburst <= S_AXI_ARBURST;
|
|
axi_arlen <= S_AXI_ARLEN;
|
|
// start address of transfer
|
|
axi_arlen_cntr <= 0;
|
|
axi_rlast <= 1'b0;
|
|
end
|
|
else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && S_AXI_RREADY)
|
|
begin
|
|
|
|
axi_arlen_cntr <= axi_arlen_cntr + 1;
|
|
axi_rlast <= 1'b0;
|
|
|
|
case (axi_arburst)
|
|
2'b00: // fixed burst
|
|
// The read address for all the beats in the transaction are fixed
|
|
begin
|
|
axi_araddr <= axi_araddr;
|
|
//for arsize = 4 bytes (010)
|
|
end
|
|
2'b01: //incremental burst
|
|
// The read address for all the beats in the transaction are increments by awsize
|
|
begin
|
|
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
|
|
//araddr aligned to 4 byte boundary
|
|
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
|
|
//for awsize = 4 bytes (010)
|
|
end
|
|
2'b10: //Wrapping burst
|
|
// The read address wraps when the address reaches wrap boundary
|
|
if (ar_wrap_en)
|
|
begin
|
|
axi_araddr <= (axi_araddr - ar_wrap_size);
|
|
end
|
|
else
|
|
begin
|
|
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
|
|
//araddr aligned to 4 byte boundary
|
|
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
|
|
end
|
|
default: //reserved (incremental burst for example)
|
|
begin
|
|
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
|
|
//for arsize = 4 bytes (010)
|
|
end
|
|
endcase
|
|
end
|
|
else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag )
|
|
begin
|
|
axi_rlast <= 1'b1;
|
|
end
|
|
else if (S_AXI_RREADY)
|
|
begin
|
|
axi_rlast <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
// Implement axi_arvalid generation
|
|
|
|
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
|
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
|
// data are available on the axi_rdata bus at this instance. The
|
|
// assertion of axi_rvalid marks the validity of read data on the
|
|
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
|
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
|
// cleared to zero on reset (active low).
|
|
|
|
always @( posedge S_AXI_ACLK )
|
|
begin
|
|
if ( S_AXI_ARESETN == 1'b0 )
|
|
begin
|
|
axi_rvalid <= 0;
|
|
axi_rresp <= 0;
|
|
end
|
|
else
|
|
begin
|
|
if (axi_arv_arr_flag && ~axi_rvalid)
|
|
begin
|
|
axi_rvalid <= 1'b1;
|
|
axi_rresp <= 2'b0;
|
|
// 'OKAY' response
|
|
end
|
|
else if (axi_rvalid && S_AXI_RREADY)
|
|
begin
|
|
axi_rvalid <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
// ------------------------------------------
|
|
// -- Example code to access user logic memory region
|
|
// ------------------------------------------
|
|
|
|
generate
|
|
if (USER_NUM_MEM >= 1)
|
|
begin
|
|
assign mem_select = 1;
|
|
assign mem_address = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
|
|
end
|
|
endgenerate
|
|
|
|
// implement Block RAM(s)
|
|
generate
|
|
for(i=0; i<= USER_NUM_MEM-1; i=i+1)
|
|
begin:BRAM_GEN
|
|
wire mem_rden;
|
|
wire mem_wren;
|
|
|
|
assign mem_wren = axi_wready && S_AXI_WVALID ;
|
|
|
|
assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid
|
|
|
|
for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
|
|
begin:BYTE_BRAM_GEN
|
|
wire [8-1:0] data_in ;
|
|
wire [8-1:0] data_out;
|
|
reg [8-1:0] byte_ram [0 : 15];
|
|
integer j;
|
|
|
|
//assigning 8 bit data
|
|
assign data_in = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
|
|
assign data_out = byte_ram[mem_address];
|
|
|
|
always @( posedge S_AXI_ACLK )
|
|
begin
|
|
if (mem_wren && S_AXI_WSTRB[mem_byte_index])
|
|
begin
|
|
byte_ram[mem_address] <= data_in;
|
|
end
|
|
end
|
|
|
|
always @( posedge S_AXI_ACLK )
|
|
begin
|
|
if (mem_rden)
|
|
begin
|
|
mem_data_out[i][(mem_byte_index*8+7) -: 8] <= data_out;
|
|
end
|
|
end
|
|
|
|
end
|
|
end
|
|
endgenerate
|
|
//Output register or memory read data
|
|
|
|
always @( mem_data_out, axi_rvalid)
|
|
begin
|
|
if (axi_rvalid)
|
|
begin
|
|
// Read address mux
|
|
axi_rdata <= mem_data_out[0];
|
|
end
|
|
else
|
|
begin
|
|
axi_rdata <= 32'h00000000;
|
|
end
|
|
end
|
|
|
|
// Add user logic here
|
|
|
|
// User logic ends
|
|
|
|
endmodule
|