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106 lines
2.7 KiB
Verilog
106 lines
2.7 KiB
Verilog
//--------------------------------------------------------------------------------
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// UartRx.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Straightforward yet simple UART receiver implementation for FPGA written in Verilog
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// Expects at least one stop bit
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// Features continuous data aquisition at BAUD levels up to CLK_HZ / 2
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// Features early asynchronous 'busy' reset
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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UartRx UR1 (
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.clk(),
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.nrst( 1'b1 ),
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.rx_data(),
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.rx_busy(),
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.rx_done(),
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.rx_err(),
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.rxd()
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);
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defparam UR1.CLK_HZ = 200_000_000;
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defparam UR1.BAUD = 9600; // max. BAUD is CLK_HZ / 2
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--- INSTANTIATION TEMPLATE END ---*/
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module UartRx(clk, nrst, rx_data, rx_busy, rx_done, rx_err, rxd);
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parameter CLK_HZ = 200_000_000;
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parameter BAUD = 9600;
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parameter BAUD_DIVISOR_2 = CLK_HZ / BAUD / 2;
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input wire clk;
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input wire nrst;
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output reg [7:0] rx_data = 0;
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reg rx_data_9th_bit = 0; // {rx_data[7:0],rx_data_9th_bit} is actually a shift register
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output reg rx_busy = 0;
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output wire rx_done; // read strobe
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output wire rx_err;
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input wire rxd;
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StaticDelay SD (
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.clk(clk),
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.nrst(nrst),
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.in(rxd),
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.out(s_rxd) // Synchronized rxd
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);
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defparam SD.LENGTH = 2;
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defparam SD.WIDTH = 1;
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reg rxd_prev = 0;
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always @ (posedge clk) begin
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if (~nrst) begin
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rxd_prev <= 0;
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end else begin
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rxd_prev <= s_rxd;
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end
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end
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wire start_bit_strobe = ~s_rxd & rxd_prev;
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reg [15:0] rx_sample_cntr = (BAUD_DIVISOR_2 - 1);
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wire rx_do_sample = (rx_sample_cntr[15:0] == 0);
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always @ (posedge clk) begin
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if (~nrst) begin
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rx_busy <= 0;
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end else begin
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if (~rx_busy) begin
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if (start_bit_strobe) begin
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rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 3 - 1); // wait for 1,5-bit period till next sample
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{rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;
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rx_busy <= 1;
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end // start_bit_strobe
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end else begin
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if (rx_sample_cntr[15:0] == 0) begin
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rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1); // wait for 1-bit-period till next sample
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end else begin
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rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1; // counting and sampling only when 'busy'
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end
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if (rx_do_sample) begin
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if (rx_data_9th_bit == 1) begin
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rx_busy <= 0; // early asynchronous 'busy' reset
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end else begin
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{rx_data[7:0],rx_data_9th_bit} <= {s_rxd, rx_data[7:0]};
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end //
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end // rx_do_sample
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end // ~rx_busy
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end // ~nrst
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end
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assign
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rx_done = rx_data_9th_bit && rx_do_sample && s_rxd, // rx_done and rx_busy fall simultaneously
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rx_err = rx_data_9th_bit && rx_do_sample && ~s_rxd;
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endmodule
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