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224 lines
8.5 KiB
Verilog
224 lines
8.5 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-28-2008
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module gearbox_67_40 (
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input clk,arst,
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input [66:0] din,
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output din_ready,
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output reg [39:0] dout
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);
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// input reg
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reg [66:0] din_r;
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always @(posedge clk or posedge arst) begin
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if (arst) din_r <= 0;
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else if (din_ready) din_r <= din;
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end
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// where are we in the schedule?
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reg [6:0] phase;
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always @(posedge clk or posedge arst) begin
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if (arst) phase <= 0;
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else begin
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if (phase == 66) phase <= 0;
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else phase <= phase + 1'b1;
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end
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end
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// shift the input word left to enter storage at the right place
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reg [96:0] positioned_data;
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reg [3:0] dshift /* synthesis preserve */;
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always @(posedge clk or posedge arst) begin
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if (arst) positioned_data <= 0;
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else begin
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case (dshift)
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4'h0 : positioned_data <= din_r << 0;
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4'h1 : positioned_data <= din_r << 1;
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4'h2 : positioned_data <= din_r << 2;
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4'h3 : positioned_data <= din_r << 3;
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4'h4 : positioned_data <= din_r << 4;
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4'h5 : positioned_data <= din_r << 13;
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4'h6 : positioned_data <= din_r << 14;
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4'h7 : positioned_data <= din_r << 15;
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4'h8 : positioned_data <= din_r << 16;
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4'h9 : positioned_data <= din_r << 17;
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4'ha : positioned_data <= din_r << 26;
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4'hb : positioned_data <= din_r << 27;
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4'hc : positioned_data <= din_r << 28;
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4'hd : positioned_data <= din_r << 29;
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4'he : positioned_data <= din_r << 30;
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4'hf : positioned_data <= 0; // no din on this tick
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endcase
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end
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end
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assign din_ready = ~&dshift;
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// on every tick shift storage left by one of a couple of distance
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// choices, and merge in the positioned data
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reg [105:0] storage;
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reg sshift /* synthesis preserve */;
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always @(posedge clk or posedge arst) begin
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if (arst) storage <= 0;
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else begin
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case (sshift)
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1'b0 : storage <= (storage << 40) | positioned_data;
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1'b1 : storage <= (storage << 45) | positioned_data;
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endcase
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end
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end
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// extract an output word from one of a couple of choices
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reg [1:0] epoint /* synthesis preserve */;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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dout <= 0;
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end
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else begin
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case (epoint)
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2'b00: dout <= storage [95:95-39];
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2'b01: dout <= storage [100:100-39];
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2'b10: dout <= storage [105:105-39];
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// this one is don't care
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2'b11: dout <= storage [105:105-39];
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endcase
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end
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end
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// The schedule - expected to map into one 6LUT per output bit
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// if it goes to ROM be sure to suppress
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reg [3:0] ds /* synthesis preserve */;
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reg [3:0] dsalt;
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reg ss /* synthesis preserve */;
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reg [1:0] ep /* synthesis preserve */;
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reg ssalt;
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reg [1:0] epalt;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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ds <= 0;
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dsalt <= 0;
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ss <= 0;
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ssalt <= 0;
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ep <= 0;
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epalt <= 0;
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end
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else begin
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case (phase[5:0])
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6'h00 : begin ds <= 4'h2; ss <= 1'h0; ep <= 2'h2; end
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6'h01 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h02 : begin ds <= 4'h7; ss <= 1'h0; ep <= 2'h0; end
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6'h03 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h04 : begin ds <= 4'hc; ss <= 1'h0; ep <= 2'h0; end
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6'h05 : begin ds <= 4'h1; ss <= 1'h0; ep <= 2'h0; end
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6'h06 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h07 : begin ds <= 4'h6; ss <= 1'h0; ep <= 2'h0; end
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6'h08 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h09 : begin ds <= 4'hb; ss <= 1'h0; ep <= 2'h0; end
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6'h0a : begin ds <= 4'h0; ss <= 1'h0; ep <= 2'h0; end
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6'h0b : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h0c : begin ds <= 4'h5; ss <= 1'h0; ep <= 2'h0; end
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6'h0d : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h0; end
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6'h0e : begin ds <= 4'ha; ss <= 1'h0; ep <= 2'h0; end
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6'h0f : begin ds <= 4'h4; ss <= 1'h0; ep <= 2'h0; end
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6'h10 : begin ds <= 4'hf; ss <= 1'h1; ep <= 2'h0; end
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6'h11 : begin ds <= 4'h9; ss <= 1'h0; ep <= 2'h1; end
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6'h12 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h13 : begin ds <= 4'he; ss <= 1'h0; ep <= 2'h1; end
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6'h14 : begin ds <= 4'h3; ss <= 1'h0; ep <= 2'h1; end
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6'h15 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h16 : begin ds <= 4'h8; ss <= 1'h0; ep <= 2'h1; end
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6'h17 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h18 : begin ds <= 4'hd; ss <= 1'h0; ep <= 2'h1; end
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6'h19 : begin ds <= 4'h2; ss <= 1'h0; ep <= 2'h1; end
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6'h1a : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h1b : begin ds <= 4'h7; ss <= 1'h0; ep <= 2'h1; end
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6'h1c : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h1d : begin ds <= 4'hc; ss <= 1'h0; ep <= 2'h1; end
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6'h1e : begin ds <= 4'h1; ss <= 1'h0; ep <= 2'h1; end
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6'h1f : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h20 : begin ds <= 4'h6; ss <= 1'h0; ep <= 2'h1; end
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6'h21 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h22 : begin ds <= 4'hb; ss <= 1'h0; ep <= 2'h1; end
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6'h23 : begin ds <= 4'h0; ss <= 1'h0; ep <= 2'h1; end
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6'h24 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h25 : begin ds <= 4'h5; ss <= 1'h0; ep <= 2'h1; end
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6'h26 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h1; end
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6'h27 : begin ds <= 4'ha; ss <= 1'h0; ep <= 2'h1; end
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6'h28 : begin ds <= 4'h4; ss <= 1'h0; ep <= 2'h1; end
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6'h29 : begin ds <= 4'hf; ss <= 1'h1; ep <= 2'h1; end
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6'h2a : begin ds <= 4'h9; ss <= 1'h0; ep <= 2'h2; end
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6'h2b : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h2c : begin ds <= 4'he; ss <= 1'h0; ep <= 2'h2; end
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6'h2d : begin ds <= 4'h3; ss <= 1'h0; ep <= 2'h2; end
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6'h2e : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h2f : begin ds <= 4'h8; ss <= 1'h0; ep <= 2'h2; end
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6'h30 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h31 : begin ds <= 4'hd; ss <= 1'h0; ep <= 2'h2; end
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6'h32 : begin ds <= 4'h2; ss <= 1'h0; ep <= 2'h2; end
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6'h33 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h34 : begin ds <= 4'h7; ss <= 1'h0; ep <= 2'h2; end
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6'h35 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h36 : begin ds <= 4'hc; ss <= 1'h0; ep <= 2'h2; end
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6'h37 : begin ds <= 4'h1; ss <= 1'h0; ep <= 2'h2; end
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6'h38 : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h39 : begin ds <= 4'h6; ss <= 1'h0; ep <= 2'h2; end
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6'h3a : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h3b : begin ds <= 4'hb; ss <= 1'h0; ep <= 2'h2; end
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6'h3c : begin ds <= 4'h0; ss <= 1'h0; ep <= 2'h2; end
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6'h3d : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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6'h3e : begin ds <= 4'h5; ss <= 1'h0; ep <= 2'h2; end
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6'h3f : begin ds <= 4'hf; ss <= 1'h0; ep <= 2'h2; end
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endcase
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case (phase[1:0])
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2'h0 : begin dsalt <= 4'ha; ssalt <= 1'h0; epalt <= 2'h2; end
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2'h1 : begin dsalt <= 4'hf; ssalt <= 1'h0; epalt <= 2'h2; end
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2'h2 : begin dsalt <= 4'hd; ssalt <= 1'h0; epalt <= 2'h2; end
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// this one is actually don't care
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2'h3 : begin dsalt <= 4'hd; ssalt <= 1'h0; epalt <= 2'h2; end
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endcase
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end
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end
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// phase 64,5,6 use the alternate schedule
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reg use_alt;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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sshift <= 0;
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dshift <= 0;
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epoint <= 0;
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use_alt <= 0;
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end
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else begin
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sshift <= use_alt ? ssalt : ss;
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dshift <= use_alt ? dsalt : ds;
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epoint <= use_alt ? epalt : ep;
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use_alt <= phase[6];
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end
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end
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endmodule
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