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130 lines
3.6 KiB
Systemverilog
130 lines
3.6 KiB
Systemverilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 09-25-2008
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// sanity checking and diagnostics for the CRC32c
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module crc32c_tb ();
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wire [1:0] status_bits = 2'b00;
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wire [63:0] sync_word = 64'h78f678f678f678f6;
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wire [63:0] scram_state = {6'b001010,58'h0};
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wire [63:0] skip_word = {6'b000111,58'h0};
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wire [63:0] diag = {6'b011001,24'h000000,status_bits,32'h00000000};
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wire [31:0] cc0_out,cc1_out,cc2_out,cc3_out,cc4_out,cc5_out;
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// first stage
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crc32c_dat64 cc0 (
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.crc_in(32'hffffffff),
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.dat_in(sync_word),
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.crc_out(cc0_out)
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);
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defparam cc0 .METHOD = 0;
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// alternate first stage
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wire [31:0] sync_word_evolved, f_evolved, cc0_alt_out;
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crc32c_dat64_only cc_a0 (.d(sync_word),.crc_out(sync_word_evolved));
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defparam cc_a0 .METHOD = 0;
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crc32c_zer64 cc_a1 (.c(32'hffffffff),.crc_out(f_evolved));
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defparam cc_a1 .METHOD = 0;
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assign cc0_alt_out = sync_word_evolved ^ f_evolved;
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// second stage
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crc32c_dat64 cc1 (
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.crc_in(cc0_out),
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.dat_in(scram_state),
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.crc_out(cc1_out)
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);
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defparam cc1 .METHOD = 1;
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crc32c_dat64 cc2 (
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.crc_in(cc1_out),
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.dat_in(skip_word),
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.crc_out(cc2_out)
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);
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defparam cc2 .METHOD = 0;
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crc32c_dat64 cc3 (
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.crc_in(cc2_out),
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.dat_in(64'hb5),
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.crc_out(cc3_out)
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);
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defparam cc3 .METHOD = 1;
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crc32c_dat64 cc4 (
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.crc_in(32'h21e1cebf),
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.dat_in(64'hba),
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.crc_out(cc4_out)
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);
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defparam cc4 .METHOD = 0;
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crc32c_dat64 cc5 (
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.crc_in(cc4_out),
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.dat_in(diag),
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.crc_out(cc5_out)
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);
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defparam cc5 .METHOD = 0;
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// alternate cc5
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wire [31:0] diag_evolved,a6_out, alt_cc5_out;
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crc32c_dat64_only cc_a5 (.d(diag),.crc_out(diag_evolved));
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defparam cc_a5 .METHOD = 1;
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crc32c_zer64 cc_a6 (.c(cc4_out),.crc_out(a6_out));
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defparam cc_a6 .METHOD = 1;
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assign alt_cc5_out = a6_out ^ diag_evolved;
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wire [31:0] cc6_out;
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crc32c_dat64 cc6 (
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.crc_in(cc4_out),
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.dat_in(diag | (32'h2bdb65fc)), // ^ 32'hffffffff)),
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.crc_out(cc6_out)
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);
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defparam cc6 .METHOD = 0;
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initial begin
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#5
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if (cc0_out !== cc0_alt_out ||
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cc5_out !== alt_cc5_out) begin
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$display ("The decomposition into data and crc halves is incorrect");
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$stop();
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end
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$display ("CRC 32c of first 3 words is %x",cc2_out);
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if (cc2_out !== 32'hd49b6ab8) begin
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$display ("There is something wrong with the polynomial / XOR network");
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$stop();
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end
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#5 $display ("PASS");
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$stop();
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end
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endmodule
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