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103 lines
3.2 KiB
Verilog
103 lines
3.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 3-15-2006
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module sha_padding (
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clk,
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reset,
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word_in,
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word_in_bits,
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word_out,
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msg_complete,
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next_word
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);
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`include "log2.inc"
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parameter WORD_SIZE = 64;
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parameter LOG_WORD = log2(WORD_SIZE-1);
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parameter WPM = 1024 / WORD_SIZE; // words per message block
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parameter LOG_WPM = log2(WPM-1);
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input clk,reset;
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input [WORD_SIZE-1:0] word_in;
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input [LOG_WORD:0] word_in_bits; // one bit too many, for full blocks
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wire word_in_full = word_in_bits[LOG_WORD];
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output [WORD_SIZE-1:0] word_out;
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input next_word;
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output msg_complete;
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reg [2*WORD_SIZE-1:0] user_bits;
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reg [LOG_WPM-1:0] words;
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// status flags for the postamble
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reg msg_size_h, msg_size_l, finishing;
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always @(posedge clk) begin
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if (reset) begin
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user_bits <= 0;
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words <= 0;
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msg_size_h <= 1'b0;
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msg_size_l <= 1'b0;
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finishing <= 1'b0;
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end
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else if (next_word) begin
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user_bits <= user_bits + word_in_bits;
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words <= words + 1'b1;
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if (!word_in_full) begin
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finishing <= 1'b1;
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if (words == (WPM-3)) msg_size_h <= 1'b1;
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end
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msg_size_l <= msg_size_h;
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end
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end
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reg [WORD_SIZE:0] one_pos;
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always @(*) begin
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one_pos = 0;
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one_pos[WORD_SIZE-1-word_in_bits] = 1'b1;
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end
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// generate the word with 1000 ... at the end if appro
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wire [WORD_SIZE-1:0] used /* synthesis keep */;
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wire [WORD_SIZE-1:0] masked_word;
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genvar i;
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generate
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for (i=0; i<WORD_SIZE; i=i+1)
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begin : mask
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assign used[i] = ((WORD_SIZE-1-word_in_bits) < i);
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assign masked_word[i] = ((word_in_full | used[i]) ? word_in[i] : 1'b0);
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end
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endgenerate
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// generate zero words, and the final message size words
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wire [WORD_SIZE-1:0] tail_word;
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assign tail_word = msg_size_l ? user_bits [WORD_SIZE-1:0] :
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msg_size_h ? user_bits [2*WORD_SIZE-1:WORD_SIZE] :
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{WORD_SIZE{1'b0}};
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assign word_out = finishing ? tail_word : (masked_word | one_pos);
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assign msg_complete = msg_size_l;
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endmodule |