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118 lines
3.1 KiB
Verilog
118 lines
3.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// test the padding of the standard demo with one byte removed
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module sha_padding_b_tb ();
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reg clk,reset;
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reg [63:0] word_in,word_expect,reg_word_out;
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reg [6:0] word_in_bits;
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reg next_word;
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wire [63:0] word_out;
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wire msg_complete;
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sha_padding sp (
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.clk(clk),
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.reset(reset),
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.word_in(word_in),
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.word_in_bits(word_in_bits),
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.word_out(word_out),
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.msg_complete(msg_complete),
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.next_word(next_word)
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);
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reg [887:0] test_str = {"abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn",
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"hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrst"};
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reg [135:0] test_str_padding = {1'b1,7'b0,
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64'h0,64'h378};
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reg [1023:0] expect_str;
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integer n;
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reg fail;
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always @(posedge clk) begin
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reg_word_out <= word_out;
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end
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initial begin
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clk = 1'b0;
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reset = 1'b1;
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fail = 1'b0;
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expect_str = {test_str,test_str_padding};
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@(posedge clk);
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@(negedge clk) reset = 1'b0;
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next_word = 1'b1;
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for (n=0; n<14; n=n+1)
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begin
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word_in = test_str [887:824];
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word_expect = expect_str [1023:960];
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word_in_bits = (n == 13 ? 7'd56 :7'd64);
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#1
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test_str = test_str << 64;
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expect_str = expect_str << 64;
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@(posedge clk);
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#1
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if (word_expect !== reg_word_out) begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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@(negedge clk);
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end
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word_in_bits = 7'd0;
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for (n=0; n<2; n=n+1)
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begin
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word_expect = expect_str [1023:960];
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expect_str = expect_str << 64;
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@(posedge clk);
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#1
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if (word_expect !== reg_word_out) begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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@(negedge clk);
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end
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if (!msg_complete) begin
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$display ("Mismatch on message complete");
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fail = 1'b1;
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end
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if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#100 clk = ~clk;
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end
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endmodule
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