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57 lines
1.9 KiB
Systemverilog
57 lines
1.9 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-15-2008
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// Simultate the pn2112 sequence to build a little table
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module pn2112_tb ();
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`include "reverse_32.inc"
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reg [0:2111] seq;
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reg clk = 0;
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reg [57:0] lfreg = 58'h2aaaaaaaaaaaaaa;
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wire out;
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assign out = (lfreg[57] ^ lfreg[38]);
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always @(posedge clk) begin
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lfreg <= {lfreg[56:0],out};
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seq <= (seq << 1) | out;
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end
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always begin
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#5 clk = ~clk;
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end
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integer n = 0;
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initial begin
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#21120
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for (n=0; n<66; n=n+1)
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begin
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$display ("7'd%d : seq = 32'h%x;",n[6:0],reverse_32(seq[32*n+:32]));
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end
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#5 $stop();
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end
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endmodule
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