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71 lines
2.3 KiB
Verilog
71 lines
2.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module barrel_shift (din,dout,distance);
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`include "log2.inc"
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parameter RIGHT = 1;
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parameter WIDTH = 16;
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parameter DIST_WIDTH = log2(WIDTH-1);
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parameter GENERIC = 0;
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localparam MAX_D = 1 << DIST_WIDTH; // The shifting range described by
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// the distance.
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input [WIDTH-1:0] din;
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output [WIDTH-1:0] dout;
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input [DIST_WIDTH-1:0] distance;
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wire [WIDTH-1:0] din_int, dout_int;
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// input reversal for ROL
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genvar i;
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generate
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if (RIGHT) assign din_int = din;
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else begin
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for (i=0; i<WIDTH; i=i+1)
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begin : revi
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assign din_int[i] = din[WIDTH-1-i];
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end
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end
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endgenerate
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// rotate right sorting network
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rotate_internal r (.din(din_int),.dout(dout_int),.distance(distance));
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defparam r .WIDTH = WIDTH;
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defparam r .DIST_WIDTH = DIST_WIDTH;
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defparam r .GENERIC = GENERIC;
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// output reversal for ROL
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generate
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if (RIGHT) assign dout = dout_int;
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else begin
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for (i=0; i<WIDTH; i=i+1)
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begin : revo
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assign dout[i] = dout_int[WIDTH-1-i];
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end
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end
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endgenerate
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endmodule
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