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66 lines
2.2 KiB
Systemverilog
66 lines
2.2 KiB
Systemverilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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module mlab_delay_tb ();
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parameter BITS_PER_WORD = 9;
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parameter WORDS = 46;
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reg clk = 0;
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reg [WORDS * BITS_PER_WORD - 1 : 0] din = 0;
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wire [WORDS * BITS_PER_WORD - 1 : 0] dout;
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reg ena = 1'b1;
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wire parity_error;
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mlab_delay dut (.*);
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defparam dut .WORDS = WORDS;
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defparam dut .BITS_PER_WORD = BITS_PER_WORD;
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defparam dut .LATENCY = 10;
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always @(posedge clk) begin
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if (ena) din <= din + 1'b1;
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end
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always @(negedge clk) ena = $random();
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reg [WORDS * BITS_PER_WORD - 1 : 0] delta;
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always @(posedge clk) delta <= din - dout;
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always begin
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#5 clk = ~clk;
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end
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reg fail = 0;
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always @(posedge clk) begin
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if (!parity_error && delta != 10) fail = 1'b1;
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end
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initial begin
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#10
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@(negedge parity_error);
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#100000
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if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |