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basic_verilog/KCPSM6_Release9_30Sept14/Reference_Designs/ICAP/ram_4096x8.vhd

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--
-------------------------------------------------------------------------------------------
-- Copyright <20> 2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Single Port RAM
-- 4096 x 8-bits
-- One RAMB36E1 primitive
--
-- Ken Chapman
-- Xilinx UK
-- 24th July 2014
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity ram_4096x8 is
Port ( address : in std_logic_vector(11 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
we : in std_logic;
clk : in std_logic);
end ram_4096x8;
--
architecture low_level_definition of ram_4096x8 is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal we_a : std_logic_vector(3 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
--
begin
--
address_a <= '1' & address(11 downto 0) & "111";
data_in_a <= "000" & data_out_a(32) & "000000000000000000000000" & data_in;
we_a <= we & we & we & we;
data_out <= data_out_a(7 downto 0);
--
address_b <= "1111111111111111";
data_in_b <= "000" & data_out_b(32) & "000000000000000000000000" & data_out_b(7 downto 0);
--
ram_4096x8: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
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port map( ADDRARDADDR => address_a,
ENARDEN => '1',
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => we_a,
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '0',
CLKBWRCLK => '0',
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE ram_4096x8.vhd
--
------------------------------------------------------------------------------------
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