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https://github.com/pConst/basic_verilog.git
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66 lines
1.6 KiB
Systemverilog
66 lines
1.6 KiB
Systemverilog
//------------------------------------------------------------------------------
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// main.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Test project template, v2
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//
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// - use this as a boilerplate project for fast prototyping
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// - inputs and outputs are registered to allow valid timequest output
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// even if your custom logic/IPs have combinational outputs
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// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
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// the fastest possible circuit
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//
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`define WIDTH
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module main(
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input clk,
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input nrst,
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input [`WIDTH-1:0] in_data,
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output logic [`WIDTH-1:0] out_data
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);
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// input registers
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logic [`WIDTH-1:0] in_data_reg = 0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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in_data_reg <= '0;
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end else begin
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in_data_reg <= in_data;
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end
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end
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// place your test logic here ==================================================
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// logic [31:0] divided_clk;
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// clk_divider #(
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// .WIDTH( 32 )
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// ) cd1 (
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// .clk( clk ),
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// .nrst( nrst ),
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// .ena( 1'b1 ),
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// .out( divided_clk[31:0] )
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// );
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// logic [`WIDTH-1:0] out_data_comb = 0;
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// always_comb begin
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// out_data_comb <= out_data_comb[`WIDTH-1:0] ^ divided_clk[31:0];
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// end
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// =============================================================================
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// output registers
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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out_data[`WIDTH-1:0] <= '0;
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end else begin
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out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
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end
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end
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endmodule |