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15 lines
680 B
Tcl
15 lines
680 B
Tcl
#------------------------------------------------------------------------------
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# allow_undefined_ports.tcl
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# Use this script for Xilinx Vivado environment to allow generation of test
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# projects with undefines pins (that will eventually have DEFAULT positional
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# and electrical standard constraints)
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#
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# Set this script as a pre.tcl for "Generate bitstream" step
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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