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https://github.com/pConst/basic_verilog.git
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181 lines
7.5 KiB
Verilog
181 lines
7.5 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//
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// 24 bit CRC of 64 data bits (reversed - MSB first)
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// polynomial : 00328b63
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// x^21 + x^20 + x^17 + x^15 + x^11 + x^9 + x^8 + x^6 + x^5 + x^1 + x^0
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//
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// CCCCCCCCCCCCCCCCCCCCCCCC DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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// 000000000011111111112222 0000000000111111111122222222223333333333444444444455555555556666
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// 012345678901234567890123 0123456789012345678901234567890123456789012345678901234567890123
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// C00 = #..#.....#....##...##.## ................................................................
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// C01 = .#.##....##...#.#..#.##. ................................................................
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// C02 = #.#.##....##...#.#..#.## ................................................................
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// C03 = .#.#.##....##...#.#..#.# ................................................................
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// C04 = #.#.#.##....##...#.#..#. ................................................................
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// C05 = ##...#.###...#.#..##..#. ................................................................
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// C06 = .###..#.#.#....##.....#. ................................................................
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// C07 = #.###..#.#.#....##.....# ................................................................
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// C08 = .#..##..###.#.##.####.## ................................................................
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// C09 = #.##.##...##.##.#.#..##. ................................................................
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// C10 = ##.##.##...##.##.#.#..## ................................................................
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// C11 = ######.###..###.#.##..#. ................................................................
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// C12 = .######.###..###.#.##..# ................................................................
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// C13 = ..######.###..###.#.##.. ................................................................
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// C14 = #..######.###..###.#.##. ................................................................
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// C15 = ##.######..#########.... ................................................................
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// C16 = .##.######..#########... ................................................................
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// C17 = #.#..####.#..#..###..### ................................................................
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// C18 = ##.#..####.#..#..###..## ................................................................
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// C19 = .##.#..####.#..#..###..# ................................................................
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// C20 = ..#..#..#.##.####....### ................................................................
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// C21 = #.....#....##...##.##... ................................................................
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// C22 = .#.....#....##...##.##.. ................................................................
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// C23 = ..#.....#....##...##.##. ................................................................
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//
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// Number of XORs used is 24
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// Maximum XOR input count is 17
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// Best possible depth in 4 LUTs = 3
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// Best possible depth in 5 LUTs = 2
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// Best possible depth in 6 LUTs = 2
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// Total XOR inputs 296
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//
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// Special signal relations -
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// none
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//
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module crc24_zer64x2_flat (c,crc_out);
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input[23:0] c;
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output[23:0] crc_out;
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wire[23:0] crc_out;
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assign crc_out[0] =
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c[0] ^ c[3] ^ c[9] ^ c[14] ^ c[15] ^ c[19] ^
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c[20] ^ c[22] ^ c[23];
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assign crc_out[1] =
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c[1] ^ c[3] ^ c[4] ^ c[9] ^ c[10] ^ c[14] ^
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c[16] ^ c[19] ^ c[21] ^ c[22];
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assign crc_out[2] =
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c[0] ^ c[2] ^ c[4] ^ c[5] ^ c[10] ^ c[11] ^
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c[15] ^ c[17] ^ c[20] ^ c[22] ^ c[23];
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assign crc_out[3] =
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c[1] ^ c[3] ^ c[5] ^ c[6] ^ c[11] ^ c[12] ^
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c[16] ^ c[18] ^ c[21] ^ c[23];
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assign crc_out[4] =
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c[0] ^ c[2] ^ c[4] ^ c[6] ^ c[7] ^ c[12] ^
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c[13] ^ c[17] ^ c[19] ^ c[22];
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assign crc_out[5] =
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c[0] ^ c[1] ^ c[5] ^ c[7] ^ c[8] ^ c[9] ^
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c[13] ^ c[15] ^ c[18] ^ c[19] ^ c[22];
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assign crc_out[6] =
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c[1] ^ c[2] ^ c[3] ^ c[6] ^ c[8] ^ c[10] ^
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c[15] ^ c[16] ^ c[22];
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assign crc_out[7] =
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c[0] ^ c[2] ^ c[3] ^ c[4] ^ c[7] ^ c[9] ^
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c[11] ^ c[16] ^ c[17] ^ c[23];
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assign crc_out[8] =
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c[1] ^ c[4] ^ c[5] ^ c[8] ^ c[9] ^ c[10] ^
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c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[18] ^ c[19] ^ c[20] ^
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c[22] ^ c[23];
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assign crc_out[9] =
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c[0] ^ c[2] ^ c[3] ^ c[5] ^ c[6] ^ c[10] ^
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c[11] ^ c[13] ^ c[14] ^ c[16] ^ c[18] ^ c[21] ^ c[22];
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assign crc_out[10] =
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c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[6] ^ c[7] ^
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c[11] ^ c[12] ^ c[14] ^ c[15] ^ c[17] ^ c[19] ^ c[22] ^
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c[23];
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assign crc_out[11] =
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c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^
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c[7] ^ c[8] ^ c[9] ^ c[12] ^ c[13] ^ c[14] ^ c[16] ^
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c[18] ^ c[19] ^ c[22];
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assign crc_out[12] =
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c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^
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c[8] ^ c[9] ^ c[10] ^ c[13] ^ c[14] ^ c[15] ^ c[17] ^
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c[19] ^ c[20] ^ c[23];
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assign crc_out[13] =
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c[2] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^
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c[9] ^ c[10] ^ c[11] ^ c[14] ^ c[15] ^ c[16] ^ c[18] ^
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c[20] ^ c[21];
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assign crc_out[14] =
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c[0] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^
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c[8] ^ c[10] ^ c[11] ^ c[12] ^ c[15] ^ c[16] ^ c[17] ^
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c[19] ^ c[21] ^ c[22];
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assign crc_out[15] =
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c[0] ^ c[1] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^
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c[7] ^ c[8] ^ c[11] ^ c[12] ^ c[13] ^ c[14] ^ c[15] ^
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c[16] ^ c[17] ^ c[18] ^ c[19];
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assign crc_out[16] =
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c[1] ^ c[2] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^
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c[8] ^ c[9] ^ c[12] ^ c[13] ^ c[14] ^ c[15] ^ c[16] ^
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c[17] ^ c[18] ^ c[19] ^ c[20];
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assign crc_out[17] =
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c[0] ^ c[2] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^
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c[10] ^ c[13] ^ c[16] ^ c[17] ^ c[18] ^ c[21] ^ c[22] ^
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c[23];
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assign crc_out[18] =
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c[0] ^ c[1] ^ c[3] ^ c[6] ^ c[7] ^ c[8] ^
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c[9] ^ c[11] ^ c[14] ^ c[17] ^ c[18] ^ c[19] ^ c[22] ^
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c[23];
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assign crc_out[19] =
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c[1] ^ c[2] ^ c[4] ^ c[7] ^ c[8] ^ c[9] ^
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c[10] ^ c[12] ^ c[15] ^ c[18] ^ c[19] ^ c[20] ^ c[23];
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assign crc_out[20] =
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c[2] ^ c[5] ^ c[8] ^ c[10] ^ c[11] ^ c[13] ^
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c[14] ^ c[15] ^ c[16] ^ c[21] ^ c[22] ^ c[23];
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assign crc_out[21] =
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c[0] ^ c[6] ^ c[11] ^ c[12] ^ c[16] ^ c[17] ^
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c[19] ^ c[20];
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assign crc_out[22] =
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c[1] ^ c[7] ^ c[12] ^ c[13] ^ c[17] ^ c[18] ^
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c[20] ^ c[21];
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assign crc_out[23] =
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c[2] ^ c[8] ^ c[13] ^ c[14] ^ c[18] ^ c[19] ^
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c[21] ^ c[22];
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endmodule
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