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257 lines
7.2 KiB
Verilog
257 lines
7.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 06-13-2006
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//
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// CRC32 of data with any size from 1 to 16 bytes (e.g. residues)
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// the input data ports typically come from the same 128 bit
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// register, but this is not a requirement.
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module crc32_dat128_any_byte (
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dat_size,
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crc_in,
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crc_out,
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dat8,dat16,dat24,dat32,
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dat40,dat48,dat56,dat64,
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dat72,dat80,dat88,dat96,
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dat104,dat112,dat120,dat128
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);
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input [3:0] dat_size;
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input [31:0] crc_in;
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output [31:0] crc_out;
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wire [31:0] crc_out;
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input [7:0] dat8;
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input [15:0] dat16;
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input [23:0] dat24;
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input [31:0] dat32;
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input [39:0] dat40;
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input [47:0] dat48;
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input [55:0] dat56;
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input [63:0] dat64;
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input [71:0] dat72;
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input [79:0] dat80;
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input [87:0] dat88;
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input [95:0] dat96;
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input [103:0] dat104;
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input [111:0] dat112;
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input [119:0] dat120;
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input [127:0] dat128;
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parameter METHOD = 1; // depth optimal factored
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parameter REVERSE_DATA = 0; // Use LSB first
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// internal data signals
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wire [7:0] dat8_w;
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wire [15:0] dat16_w;
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wire [23:0] dat24_w;
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wire [31:0] dat32_w;
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wire [39:0] dat40_w;
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wire [47:0] dat48_w;
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wire [55:0] dat56_w;
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wire [63:0] dat64_w;
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wire [71:0] dat72_w;
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wire [79:0] dat80_w;
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wire [87:0] dat88_w;
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wire [95:0] dat96_w;
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wire [103:0] dat104_w;
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wire [111:0] dat112_w;
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wire [119:0] dat120_w;
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wire [127:0] dat128_w;
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//////////////////////////////////////////////////////
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// Optional reversal of the data bits to do LSB
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// of data 1st. No area cost
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//////////////////////////////////////////////////////
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genvar i;
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generate
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if (REVERSE_DATA)
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begin
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for (i=0; i<128; i=i+1)
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begin : rev_128
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assign dat128_w[i] = dat128[127-i];
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end
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for (i=0; i<120; i=i+1)
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begin : rev_120
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assign dat120_w[i] = dat120[119-i];
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end
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for (i=0; i<112; i=i+1)
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begin : rev_112
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assign dat112_w[i] = dat112[111-i];
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end
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for (i=0; i<104; i=i+1)
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begin : rev_104
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assign dat104_w[i] = dat104[103-i];
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end
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for (i=0; i<96; i=i+1)
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begin : rev_96
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assign dat96_w[i] = dat96[95-i];
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end
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for (i=0; i<88; i=i+1)
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begin : rev_88
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assign dat88_w[i] = dat88[87-i];
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end
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for (i=0; i<80; i=i+1)
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begin : rev_80
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assign dat80_w[i] = dat80[79-i];
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end
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for (i=0; i<72; i=i+1)
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begin : rev_72
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assign dat72_w[i] = dat72[71-i];
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end
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for (i=0; i<64; i=i+1)
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begin : rev_64
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assign dat64_w[i] = dat64[63-i];
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end
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for (i=0; i<56; i=i+1)
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begin : rev_56
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assign dat56_w[i] = dat56[55-i];
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end
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for (i=0; i<48; i=i+1)
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begin : rev_48
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assign dat48_w[i] = dat48[47-i];
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end
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for (i=0; i<40; i=i+1)
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begin : rev_40
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assign dat40_w[i] = dat40[39-i];
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end
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for (i=0; i<32; i=i+1)
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begin : rev_32
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assign dat32_w[i] = dat32[31-i];
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end
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for (i=0; i<24; i=i+1)
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begin : rev_24
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assign dat24_w[i] = dat24[23-i];
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end
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for (i=0; i<16; i=i+1)
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begin : rev_16
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assign dat16_w[i] = dat16[15-i];
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end
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for (i=0; i<8; i=i+1)
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begin : rev_8
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assign dat8_w[i] = dat8[7-i];
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end
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end
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else
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begin
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// no reversal - pass along
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assign dat128_w = dat128;
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assign dat120_w = dat120;
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assign dat112_w = dat112;
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assign dat104_w = dat104;
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assign dat96_w = dat96;
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assign dat88_w = dat88;
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assign dat80_w = dat80;
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assign dat72_w = dat72;
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assign dat64_w = dat64;
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assign dat56_w = dat56;
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assign dat48_w = dat48;
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assign dat40_w = dat40;
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assign dat32_w = dat32;
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assign dat24_w = dat24;
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assign dat16_w = dat16;
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assign dat8_w = dat8;
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end
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endgenerate
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//////////////////////////////////////////////////////
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// define a parallel array of CRC units for one to
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// sixteen bytes of data.
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//////////////////////////////////////////////////////
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wire [31:0] co_a,co_b,co_c,co_d,co_e,co_f,co_g,co_h;
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wire [31:0] co_i,co_j,co_k,co_l,co_m,co_n,co_o,co_p;
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crc32_dat8 a (.crc_in (crc_in),.crc_out (co_a),.dat_in(dat8_w));
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crc32_dat16 b (.crc_in (crc_in),.crc_out (co_b),.dat_in(dat16_w));
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crc32_dat24 c (.crc_in (crc_in),.crc_out (co_c),.dat_in(dat24_w));
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crc32_dat32 d (.crc_in (crc_in),.crc_out (co_d),.dat_in(dat32_w));
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crc32_dat40 e (.crc_in (crc_in),.crc_out (co_e),.dat_in(dat40_w));
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crc32_dat48 f (.crc_in (crc_in),.crc_out (co_f),.dat_in(dat48_w));
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crc32_dat56 g (.crc_in (crc_in),.crc_out (co_g),.dat_in(dat56_w));
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crc32_dat64 h (.crc_in (crc_in),.crc_out (co_h),.dat_in(dat64_w));
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crc32_dat72 ii (.crc_in (crc_in),.crc_out (co_i),.dat_in(dat72_w));
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crc32_dat80 j (.crc_in (crc_in),.crc_out (co_j),.dat_in(dat80_w));
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crc32_dat88 k (.crc_in (crc_in),.crc_out (co_k),.dat_in(dat88_w));
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crc32_dat96 l (.crc_in (crc_in),.crc_out (co_l),.dat_in(dat96_w));
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crc32_dat104 m (.crc_in (crc_in),.crc_out (co_m),.dat_in(dat104_w));
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crc32_dat112 n (.crc_in (crc_in),.crc_out (co_n),.dat_in(dat112_w));
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crc32_dat120 o (.crc_in (crc_in),.crc_out (co_o),.dat_in(dat120_w));
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crc32_dat128 p (.crc_in (crc_in),.crc_out (co_p),.dat_in(dat128_w));
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defparam a .METHOD = METHOD;
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defparam b .METHOD = METHOD;
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defparam c .METHOD = METHOD;
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defparam d .METHOD = METHOD;
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defparam e .METHOD = METHOD;
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defparam f .METHOD = METHOD;
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defparam g .METHOD = METHOD;
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defparam h .METHOD = METHOD;
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defparam ii .METHOD = METHOD;
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defparam j .METHOD = METHOD;
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defparam k .METHOD = METHOD;
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defparam l .METHOD = METHOD;
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defparam m .METHOD = METHOD;
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defparam n .METHOD = METHOD;
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defparam o .METHOD = METHOD;
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defparam p .METHOD = METHOD;
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//////////////////////////////////////////////////////
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// select the CRC output according to data width
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//////////////////////////////////////////////////////
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generate
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for (i=0; i<32;i=i+1)
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begin : parmux
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wire [15:0] tmp_m;
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assign tmp_m[0] = co_a[i];
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assign tmp_m[1] = co_b[i];
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assign tmp_m[2] = co_c[i];
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assign tmp_m[3] = co_d[i];
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assign tmp_m[4] = co_e[i];
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assign tmp_m[5] = co_f[i];
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assign tmp_m[6] = co_g[i];
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assign tmp_m[7] = co_h[i];
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assign tmp_m[8] = co_i[i];
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assign tmp_m[9] = co_j[i];
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assign tmp_m[10] = co_k[i];
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assign tmp_m[11] = co_l[i];
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assign tmp_m[12] = co_m[i];
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assign tmp_m[13] = co_n[i];
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assign tmp_m[14] = co_o[i];
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assign tmp_m[15] = co_p[i];
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assign crc_out[i] = tmp_m[dat_size];
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end
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endgenerate
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endmodule |