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103 lines
2.8 KiB
Verilog
103 lines
2.8 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-28-2008
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module chain_delay_rand
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(
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clk,rst,
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out_bit,
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out_bit_valid,
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//debug info
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cal_a,cal_b,
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adjusting
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);
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input clk,rst;
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output reg out_bit,out_bit_valid;
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output [3:0] cal_a, cal_b;
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output adjusting;
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wire a_wins,b_wins,valid;
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wire [3:0] cal_a, cal_b;
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wire adjusting;
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// Dual carry chain delay lines
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chain_delay_race dr
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(
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.clk(clk),
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.rst(rst),
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.calibrate_a(cal_a),
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.calibrate_b(cal_b),
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.a_wins(a_wins),
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.b_wins(b_wins),
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.valid(valid)
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);
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// Control logic to adjust delays for unstable behavior
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chain_delay_adjust dm (
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.clk(clk),
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.rst(rst),
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.calibrate_a(cal_a),
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.calibrate_b(cal_b),
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.a_wins(a_wins),
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.b_wins(b_wins),
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.valid(valid),
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.adjusting(adjusting),
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.current_stats()
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);
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// output filter - to fix up duty imbalance
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reg last_a,last_b,last_valid;
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always @(posedge clk) begin
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if (rst) begin
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last_a <= 1'b0;
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last_b <= 1'b0;
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last_valid <= 1'b0;
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out_bit <= 0;
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out_bit_valid <= 0;
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end
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else begin
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out_bit_valid <= 1'b0;
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if (valid & !adjusting) begin
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if (!last_valid) begin
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last_a <= a_wins;
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last_b <= b_wins;
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last_valid <= 1'b1;
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end
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else begin
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if ({last_a,last_b} > {a_wins,b_wins}) begin
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out_bit_valid <= 1'b1;
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out_bit <= 1'b1;
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end else if ({last_a,last_b} < {a_wins,b_wins}) begin
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out_bit_valid <= 1'b1;
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out_bit <= 1'b0;
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end
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last_valid <= 1'b0;
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end
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end
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end
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end
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endmodule |