mirror of
https://github.com/pConst/basic_verilog.git
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421 lines
10 KiB
C++
421 lines
10 KiB
C++
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdlib.h>
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#include <time.h>
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void panic (char * msg)
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{
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fprintf (stdout,"PANIC: %s\n",msg);
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exit(1);
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}
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int pseudo_log2 (int val)
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{
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int ret = 0;
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while (val > 0)
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{
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ret++;
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val >>= 1;
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}
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return (ret);
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}
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int const MAX_DISPLACE = 15;
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int const PERIOD = 64;
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int const WORD_LEN = 32;
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int const HIST_WORDS = 2*MAX_DISPLACE + 1;
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int const NUM_SEL = pseudo_log2 (HIST_WORDS-1);
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int const CNTR_BITS = pseudo_log2 (PERIOD-1);
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///////////////////////////////////////////////////////////
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class SHIFT_REG
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{
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public :
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SHIFT_REG(int b)
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{
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depth = b;
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data = new int[depth];
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}
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~SHIFT_REG()
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{
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delete data;
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data = NULL;
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}
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void shift_in (int val);
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void shift_in_reversed (int val);
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int shift_out ();
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void dump ();
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int par_read (int slot);
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void par_write (int slot, int val);
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int index_of_value (int val);
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private :
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int * data;
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int depth;
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};
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void SHIFT_REG::shift_in (int val)
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{
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int n = 0;
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for (n=depth-1; n>0; n--)
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{
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data[n] = data[n-1];
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}
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data[0] = val;
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}
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void SHIFT_REG::shift_in_reversed (int val)
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{
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int n = 0;
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for (n=0; n<depth; n++)
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{
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data[n] = data[n+1];
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}
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data[depth-1] = val;
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}
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int SHIFT_REG::shift_out ()
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{
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int n = data[depth-1];
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shift_in(-1);
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return (n);
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}
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void SHIFT_REG::dump ()
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{
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int n = 0;
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for (n=0; n<depth; n++)
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{
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fprintf (stdout,"%3d ",data[n]);
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}
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fprintf (stdout,"\n");
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}
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int SHIFT_REG::par_read (int slot)
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{
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if (slot < 0 || slot >= depth)
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{
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panic ("Read out of range");
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}
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return (data[slot]);
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}
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void SHIFT_REG::par_write (int slot, int val)
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{
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if (slot < 0 || slot >= depth)
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{
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panic ("Read out of range");
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}
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data[slot] = val;
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}
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int SHIFT_REG::index_of_value (int val)
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{
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int n = 0;
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for (n=0; n<depth; n++)
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{
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if (data[n] == val) return (n);
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}
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return (-1);
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}
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///////////////////////////////////////////////////////////
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void build_scrambler
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(
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SHIFT_REG * indices,
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SHIFT_REG * data_stream
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)
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{
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int n = 0, k = 0;
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int sel_out = 0;
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bool any_late = false;
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int cycle = 0;
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int min_sel = 0;
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SHIFT_REG * shifter = NULL;
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shifter = new SHIFT_REG (2 * MAX_DISPLACE + 1);
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// initialize
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for (n=0;n<MAX_DISPLACE;n++)
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{
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shifter->shift_in (-1);
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}
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for (n=0;n<MAX_DISPLACE+1;n++)
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{
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shifter->shift_in (n);
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}
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//shifter->dump();
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// scramble
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for (n=MAX_DISPLACE+1; n<PERIOD+MAX_DISPLACE+1; n++)
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{
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// force it to recenter at the end of the period
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min_sel = 0;
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if (cycle >= (PERIOD-MAX_DISPLACE))
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{
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min_sel = MAX_DISPLACE+1 - (PERIOD-cycle);
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}
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//fprintf (stdout,"round %d - select >= %d\n",
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// cycle,min_sel);
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// select anything not -1
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sel_out = 2*MAX_DISPLACE;
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while ((sel_out < min_sel) || (shifter->par_read(sel_out) == -1))
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{
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sel_out = rand() % (2*MAX_DISPLACE);
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}
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//shifter->dump();
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//fprintf (stdout,"// step %d - out[%d] = %d\n",
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// cycle,sel_out,shifter->par_read(sel_out));
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// keep track
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data_stream->shift_in(shifter->par_read(sel_out));
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indices->shift_in(sel_out);
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cycle++;
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// advance
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shifter->par_write(sel_out,-1);
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shifter->shift_in (n);
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}
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//shifter->dump();
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}
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///////////////////////////////////////////////////////
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void build_unscrambler
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(
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SHIFT_REG * data_stream,
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SHIFT_REG * indices
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)
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{
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int n = 0, k = 0;
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int sel_out = 0;
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SHIFT_REG * shifter = NULL;
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shifter = new SHIFT_REG (2 * MAX_DISPLACE + 1);
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// initialize
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for (n=0;n<MAX_DISPLACE;n++)
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{
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shifter->shift_in (-1);
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}
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for (n=0;n<MAX_DISPLACE+1;n++)
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{
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shifter->shift_in (data_stream->shift_out());
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}
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//shifter->dump();
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for (n=0; n<PERIOD; n++)
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{
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k = shifter->index_of_value (n);
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indices->shift_in(k);
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shifter->shift_in (data_stream->shift_out());
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}
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}
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///////////////////////////////////////////////////////
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void latency_adjustment
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(
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SHIFT_REG * data,
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int bits_per_tick,
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int leading_samples
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)
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{
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// for bits per tick = 2
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// bits 0,1 have no latency
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// bits 2,3 need to rotate by 1
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// bits 4,5 need to rotate by 2
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int n = 0;
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SHIFT_REG * bit_reg [32];
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unsigned int val = 0;
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int k = 0;
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int b = 0;
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for (n=0; n<32; n++)
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{
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bit_reg[n] = new SHIFT_REG (PERIOD);
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}
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// decompose into bits
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for (k=0;k<PERIOD;k++)
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{
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val = data->shift_out();
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for (n=0; n<32; n++)
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{
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bit_reg[n]->shift_in ((val & 1) ? 1 : 0);
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val = val >> 1;
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}
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}
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// skew bits for read mux latency
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// this saves some stall registers on the select path
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for (n=bits_per_tick; n<32; n+=bits_per_tick)
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{
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for (k=n; k<32; k++)
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{
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bit_reg[k]->shift_in_reversed (bit_reg[k]->par_read(0));
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}
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}
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// put words back together
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for (k=0;k<PERIOD;k++)
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{
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val = 0;
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for (n=0; n<32; n++)
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{
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b = bit_reg[n]->shift_out();
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val |= (b << n);
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}
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data->shift_in(val);
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}
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// skew for history latency
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for (n=0; n<leading_samples; n++)
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{
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data->shift_in_reversed (data->par_read(0));
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}
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}
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///////////////////////////////////////////////////////
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int main (void)
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{
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SHIFT_REG * data_stream = NULL;
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SHIFT_REG * indices = NULL;
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SHIFT_REG * undo_indices = NULL;
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int n = 0;
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int val = 0, valb = 0;
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// srand(time(NULL));
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srand(123);
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indices = new SHIFT_REG (PERIOD);
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data_stream = new SHIFT_REG (PERIOD);
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undo_indices = new SHIFT_REG (PERIOD);
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// make scramble and unscramble patterns
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build_scrambler (indices,data_stream);
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build_unscrambler (data_stream,undo_indices);
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fprintf (stdout,"//");
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indices->dump();
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fprintf (stdout,"//");
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undo_indices->dump();
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// make verilog
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fprintf (stdout,"module word_stream_scramble (clk,rst,ena,din,dout,dout_valid);\n\n");
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fprintf (stdout,"`include \"log2.inc\"\n\n");
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fprintf (stdout,"parameter WORD_LEN = %d;\n",WORD_LEN);
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fprintf (stdout,"parameter SCRAMBLE = 1'b1; // 0 for undo\n\n");
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fprintf (stdout,"localparam HIST_WORDS = %d;\n",HIST_WORDS);
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fprintf (stdout,"localparam PERIOD = %d;\n",PERIOD);
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fprintf (stdout,"localparam NUM_SEL = log2(HIST_WORDS-1);\n");
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fprintf (stdout,"localparam CNTR_BITS = log2(PERIOD-1);\n");
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fprintf (stdout,"localparam PAD_WORDS = (1<<NUM_SEL)-HIST_WORDS;\n\n");
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fprintf (stdout,"input clk,rst,ena;\n");
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fprintf (stdout,"input [WORD_LEN-1:0] din;\n");
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fprintf (stdout,"output [WORD_LEN-1:0] dout;\n");
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fprintf (stdout,"output dout_valid;\n\n");
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fprintf (stdout,"// din history shift register\n");
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fprintf (stdout,"reg [HIST_WORDS * WORD_LEN-1 : 0] history;\n");
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fprintf (stdout,"always @(posedge clk) begin\n");
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fprintf (stdout," if (ena) begin\n");
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fprintf (stdout," if (rst) history <= 0;\n");
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fprintf (stdout," else history <= {history[(HIST_WORDS-1)*WORD_LEN-1:0],din};\n");
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fprintf (stdout," end\n");
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fprintf (stdout,"end\n\n");
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fprintf (stdout,"// parallel access pipelined read mux\n");
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fprintf (stdout,"reg [NUM_SEL-1:0] sel;\n");
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fprintf (stdout,"pipelined_word_mux pwm (\n");
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fprintf (stdout," .clk(clk), .rst(rst),.ena(ena),\n");
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fprintf (stdout," .sel(sel),\n");
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fprintf (stdout," .din({{PAD_WORDS*WORD_LEN{1'b0}},history}),\n");
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fprintf (stdout," .dout(dout));\n");
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fprintf (stdout," defparam pwm .WORD_LEN = WORD_LEN;\n");
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fprintf (stdout," defparam pwm .NUM_WORDS_IN = HIST_WORDS+PAD_WORDS;\n");
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fprintf (stdout," defparam pwm .SEL_PER_LAYER = 2;\n");
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fprintf (stdout," defparam pwm .BALANCE_SELECTS = 1'b0;\n\n");
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fprintf (stdout,"// scrambling sequence counter\n");
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fprintf (stdout,"reg [CNTR_BITS-1:0] cntr;\n");
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fprintf (stdout,"always @(posedge clk) begin\n");
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fprintf (stdout," if (ena) begin\n");
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fprintf (stdout," if (rst) cntr <= 0;\n");
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fprintf (stdout," else cntr <= cntr + 1'b1;\n");
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fprintf (stdout," end\n");
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fprintf (stdout,"end\n\n");
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// latency adjustment - the lower order selects
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// have less latency than the higher order
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latency_adjustment (indices,2,MAX_DISPLACE);
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latency_adjustment (undo_indices,2,MAX_DISPLACE);
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fprintf (stdout,"// scramble pattern table to drive read select\n");
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fprintf (stdout,"always @(posedge clk) begin\n");
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fprintf (stdout," if (ena) begin\n");
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fprintf (stdout," if (rst) sel <= 0;\n");
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fprintf (stdout," else begin\n");
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fprintf (stdout," case (cntr)\n");
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for (n=0; n<PERIOD; n++)
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{
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val = indices->shift_out();
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valb = undo_indices->shift_out();
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fprintf (stdout," %d'h%x : sel <= (SCRAMBLE ? %d'h%x : %d'h%x);\n",
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CNTR_BITS,n,NUM_SEL,val,NUM_SEL,valb);
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}
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fprintf (stdout," endcase\n");
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fprintf (stdout," end\n");
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fprintf (stdout," end\n");
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fprintf (stdout,"end\n\n");
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fprintf (stdout,"// indicate (fresh) valid output data\n");
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fprintf (stdout,"reg dout_active, dout_valid;\n");
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fprintf (stdout,"always @(posedge clk) begin\n");
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fprintf (stdout," if (ena & rst) begin\n");
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fprintf (stdout," dout_valid <= 1'b0;\n");
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fprintf (stdout," dout_active <= 1'b0;\n");
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fprintf (stdout," end else begin\n");
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fprintf (stdout," if (cntr == %d'h%x) dout_active <= 1'b1;\n",
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CNTR_BITS,MAX_DISPLACE+(CNTR_BITS/2) + (CNTR_BITS%2) - 1);
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fprintf (stdout," dout_valid <= dout_active & ena;\n");
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fprintf (stdout," end\n");
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fprintf (stdout,"end\n\n");
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fprintf (stdout,"endmodule\n");
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return (0);
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}
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