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42 lines
1.9 KiB
Verilog
42 lines
1.9 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module xor6 (out,a,b,c,d,e,f);
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input a,b,c,d,e,f;
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output out;
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wire out;
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// Equivalent function : out = a ^ b ^ c ^ d ^ e ^ f;
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//assign out = a ^ b ^ c ^ d ^ e ^ f;
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stratixii_lcell_comb s2lc (
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.dataa (a),.datab (b),.datac (c),.datad (d),.datae (e),.dataf (f),.datag(1'b1),
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.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
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.combout(out));
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defparam s2lc .lut_mask = 64'h6996966996696996;
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defparam s2lc .shared_arith = "off";
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defparam s2lc .extended_lut = "off";
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endmodule
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