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77 lines
2.4 KiB
Systemverilog
77 lines
2.4 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler -03-23-2009
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module stream_grabber_tb ();
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parameter DAT_WIDTH = 72; // multiple of 8
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parameter ADDR_BITS = 4; // depth of the sample memory
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reg clk,arst;
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reg [DAT_WIDTH-1:0] data_in = 0;
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reg data_in_valid = 1'b0;
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reg start_harvest;
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wire reporting;
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wire [7:0] byte_out;
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wire byte_out_valid;
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reg byte_out_ready = 1'b1;
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//////////////////////////////////
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// DUT
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//////////////////////////////////
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stream_grabber dut
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(
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.*
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);
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defparam dut .DAT_WIDTH = DAT_WIDTH;
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defparam dut .ADDR_BITS = ADDR_BITS;
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//////////////////////////////////
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// Rough data stream
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//////////////////////////////////
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always @(posedge clk) begin
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if (data_in_valid) data_in <= data_in + 1'b1;
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data_in_valid <= $random;
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end
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//////////////////////////////////
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// Clock driver
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//////////////////////////////////
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always begin
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#5 clk = ~clk;
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end
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initial begin
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clk = 0;
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arst = 0;
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#1 arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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#200
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@(negedge clk) start_harvest = 1'b1;
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@(negedge clk) start_harvest = 1'b0;
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end
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endmodule |