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265 lines
7.3 KiB
Systemverilog
265 lines
7.3 KiB
Systemverilog
`timescale 1 ps / 1 ps
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// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module scrambler (
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clk,
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reset,
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lane_number,
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word_is_scrambler_state,
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word_is_synchronization,
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word_is_to_be_scrambled,
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data_in,
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Data
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);
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input clk;
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input reset;
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input [3:0] lane_number;
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input word_is_scrambler_state;
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input word_is_synchronization;
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input word_is_to_be_scrambled;
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input [63:0] data_in;
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output [63:0] Data;
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reg [63:0] Data;
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reg [57:0] Poly;
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wire [63:0] next;
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assign next[63] = Poly[57] ^ Poly[38];
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assign next[62] = Poly[56] ^ Poly[37];
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assign next[61] = Poly[55] ^ Poly[36];
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assign next[60] = Poly[54] ^ Poly[35];
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assign next[59] = Poly[53] ^ Poly[34];
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assign next[58] = Poly[52] ^ Poly[33];
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assign next[57] = Poly[51] ^ Poly[32];
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assign next[56] = Poly[50] ^ Poly[31];
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assign next[55] = Poly[49] ^ Poly[30];
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assign next[54] = Poly[48] ^ Poly[29];
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assign next[53] = Poly[47] ^ Poly[28];
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assign next[52] = Poly[46] ^ Poly[27];
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assign next[51] = Poly[45] ^ Poly[26];
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assign next[50] = Poly[44] ^ Poly[25];
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assign next[49] = Poly[43] ^ Poly[24];
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assign next[48] = Poly[42] ^ Poly[23];
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assign next[47] = Poly[41] ^ Poly[22];
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assign next[46] = Poly[40] ^ Poly[21];
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assign next[45] = Poly[39] ^ Poly[20];
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assign next[44] = Poly[38] ^ Poly[19];
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assign next[43] = Poly[37] ^ Poly[18];
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assign next[42] = Poly[36] ^ Poly[17];
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assign next[41] = Poly[35] ^ Poly[16];
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assign next[40] = Poly[34] ^ Poly[15];
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assign next[39] = Poly[33] ^ Poly[14];
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assign next[38] = Poly[32] ^ Poly[13];
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assign next[37] = Poly[31] ^ Poly[12];
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assign next[36] = Poly[30] ^ Poly[11];
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assign next[35] = Poly[29] ^ Poly[10];
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assign next[34] = Poly[28] ^ Poly[9];
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assign next[33] = Poly[27] ^ Poly[8];
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assign next[32] = Poly[26] ^ Poly[7];
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assign next[31] = Poly[25] ^ Poly[6];
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assign next[30] = Poly[24] ^ Poly[5];
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assign next[29] = Poly[23] ^ Poly[4];
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assign next[28] = Poly[22] ^ Poly[3];
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assign next[27] = Poly[21] ^ Poly[2];
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assign next[26] = Poly[20] ^ Poly[1];
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assign next[25] = Poly[19] ^ Poly[0];
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assign next[24] = Poly[57] ^ Poly[38] ^ Poly[18];
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assign next[23] = Poly[56] ^ Poly[37] ^ Poly[17];
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assign next[22] = Poly[55] ^ Poly[36] ^ Poly[16];
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assign next[21] = Poly[54] ^ Poly[35] ^ Poly[15];
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assign next[20] = Poly[53] ^ Poly[34] ^ Poly[14];
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assign next[19] = Poly[52] ^ Poly[33] ^ Poly[13];
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assign next[18] = Poly[51] ^ Poly[32] ^ Poly[12];
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assign next[17] = Poly[50] ^ Poly[31] ^ Poly[11];
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assign next[16] = Poly[49] ^ Poly[30] ^ Poly[10];
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assign next[15] = Poly[48] ^ Poly[29] ^ Poly[9];
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assign next[14] = Poly[47] ^ Poly[28] ^ Poly[8];
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assign next[13] = Poly[46] ^ Poly[27] ^ Poly[7];
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assign next[12] = Poly[45] ^ Poly[26] ^ Poly[6];
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assign next[11] = Poly[44] ^ Poly[25] ^ Poly[5];
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assign next[10] = Poly[43] ^ Poly[24] ^ Poly[4];
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assign next[9] = Poly[42] ^ Poly[23] ^ Poly[3];
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assign next[8] = Poly[41] ^ Poly[22] ^ Poly[2];
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assign next[7] = Poly[40] ^ Poly[21] ^ Poly[1];
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assign next[6] = Poly[39] ^ Poly[20] ^ Poly[0];
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assign next[5] = Poly[57] ^ Poly[19];
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assign next[4] = Poly[56] ^ Poly[18];
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assign next[3] = Poly[55] ^ Poly[17];
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assign next[2] = Poly[54] ^ Poly[16];
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assign next[1] = Poly[53] ^ Poly[15];
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assign next[0] = Poly[52] ^ Poly[14];
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always @(posedge clk) begin
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if(reset) begin
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Poly <= {{54{1'b1}}, lane_number[3:0]}; //reset each lane differently
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Data <= 64'b0;
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end else if(word_is_to_be_scrambled) begin
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Poly <= next[57:0];
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Data <= data_in[63:0] ^ {Poly[57:0], next[63:58]};
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end else if(word_is_synchronization) begin
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Data <= 64'h78f678f678f678f6;
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end else if(word_is_scrambler_state) begin
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Data <= {6'b001010 , Poly[57:0]};
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end
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end
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endmodule
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///////////////////////////////////////////////////////////
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module scrambler_b (
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clk,
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reset,
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lane_number,
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word_is_scrambler_state,
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word_is_synchronization,
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word_is_to_be_scrambled,
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data_in,
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Data
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);
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input clk;
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input reset;
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input [3:0] lane_number;
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input word_is_scrambler_state;
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input word_is_synchronization;
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input word_is_to_be_scrambled;
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input [63:0] data_in;
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output [63:0] Data;
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reg [63:0] Data;
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reg [57:0] Poly;
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wire [63:0] next;
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assign next = {Poly,Poly[57:52]} ^
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{Poly[38:0],Poly[38:14]} ^
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{39'b0,Poly[57:39],6'b0};
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always @(posedge clk) begin
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if(reset) begin
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Poly <= {{54{1'b1}}, lane_number[3:0]}; //reset each lane differently
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Data <= 64'b0;
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end else if(word_is_to_be_scrambled) begin
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Poly <= next[57:0];
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Data <= data_in[63:0] ^ {Poly[57:0], next[63:58]};
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end else if(word_is_synchronization) begin
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Data <= 64'h78f678f678f678f6;
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end else if(word_is_scrambler_state) begin
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Data <= {6'b001010 , Poly[57:0]};
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end
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end
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endmodule
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///////////////////////////////////////////////////////////
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module scrambler_tb ();
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reg clk,reset;
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reg [3:0] lane_number = 2;
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reg word_is_scrambler_state = 0;
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reg word_is_synchronization = 0;
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reg word_is_to_be_scrambled = 1'b1;
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reg [63:0] data_in = 0;
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wire [63:0] Data;
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wire [63:0] Data_b;
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wire [63:0] Data_c;
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scrambler dut (
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.clk(clk),
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.reset(reset),
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.lane_number(lane_number),
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.word_is_scrambler_state(word_is_scrambler_state),
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.word_is_synchronization(word_is_synchronization),
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.word_is_to_be_scrambled(word_is_to_be_scrambled),
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.data_in(data_in),
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.Data(Data)
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);
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scrambler_b dut_b (
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.clk(clk),
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.reset(reset),
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.lane_number(lane_number),
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.word_is_scrambler_state(word_is_scrambler_state),
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.word_is_synchronization(word_is_synchronization),
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.word_is_to_be_scrambled(word_is_to_be_scrambled),
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.data_in(data_in),
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.Data(Data_b)
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);
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scrambler_lfsr dut_c (
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.clk(clk),
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.arst(reset),
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.load(1'b0),
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.verify(1'b0),
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.load_d(58'h0),
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.evolve(1'b1),
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.q(Data_c),
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.verify_pass(),
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.verify_fail()
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);
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reg [63:0] last_c;
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always @(posedge clk) begin
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if (reset) last_c <= 0;
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else last_c <= Data_c;
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end
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defparam dut_c .RESET_VAL = {{54{1'b1}}, 4'h2};
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initial begin
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clk = 0;
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reset = 1'b1;
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@(negedge clk) reset = 1'b0;
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end
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always begin
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#5 clk = ~clk;
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end
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reg fail = 0;
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always @(posedge clk) begin
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#1 if (Data !== Data_b) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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if (Data !== last_c) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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initial begin
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#10000000
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if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |