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118 lines
3.5 KiB
Verilog
118 lines
3.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-15-2007
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module vga_driver (
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r,g,b,
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current_x,current_y,request,
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vga_r,vga_g,vga_b,vga_hs,vga_vs,vga_blank,vga_clock,
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clk27,rst27);
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input [9:0] r,g,b;
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output [9:0] current_x;
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output [9:0] current_y;
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output request;
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output [9:0] vga_r, vga_g, vga_b;
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output vga_hs, vga_vs, vga_blank, vga_clock;
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input clk27, rst27;
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////////////////////////////////////////////////////////////
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// Horizontal Timing
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parameter H_FRONT = 16;
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parameter H_SYNC = 96;
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parameter H_BACK = 48;
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parameter H_ACT = 640;
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parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
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parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
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// Vertical Timing
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parameter V_FRONT = 11;
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parameter V_SYNC = 2;
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parameter V_BACK = 31;
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parameter V_ACT = 480;
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parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
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parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
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////////////////////////////////////////////////////////////
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reg [9:0] h_cntr, v_cntr, current_x, current_y;
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reg h_active, v_active, vga_hs, vga_vs;
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assign vga_blank = h_active & v_active;
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assign vga_clock = ~clk27;
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assign vga_r = r;
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assign vga_g = g;
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assign vga_b = b;
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assign request = ((h_cntr>=H_BLANK && h_cntr<H_TOTAL) &&
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(v_cntr>=V_BLANK && v_cntr<V_TOTAL));
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always @(posedge clk27) begin
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if(rst27) begin
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h_cntr <= 0;
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v_cntr <= 0;
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vga_hs <= 1'b1;
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vga_vs <= 1'b1;
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current_x <= 0;
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current_y <= 0;
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h_active <= 1'b0;
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v_active <= 1'b0;
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end
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else begin
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if(h_cntr != H_TOTAL) begin
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h_cntr <= h_cntr + 1'b1;
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if (h_active) current_x <= current_x + 1'b1;
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if (h_cntr == H_BLANK-1) h_active <= 1'b1;
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end
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else begin
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h_cntr <= 0;
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h_active <= 1'b0;
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current_x <= 0;
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end
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if(h_cntr == H_FRONT-1) begin
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vga_hs <= 1'b0;
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end
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if (h_cntr == H_FRONT+H_SYNC-1) begin
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vga_hs <= 1'b1;
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if(v_cntr != V_TOTAL) begin
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v_cntr <= v_cntr + 1'b1;
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if (v_active) current_y <= current_y + 1'b1;
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if (v_cntr == V_BLANK-1) v_active <= 1'b1;
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end
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else begin
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v_cntr <= 0;
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current_y <= 0;
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v_active <= 1'b0;
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end
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if(v_cntr == V_FRONT-1) vga_vs <= 1'b0;
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if(v_cntr == V_FRONT+V_SYNC-1) vga_vs <= 1'b1;
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end
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end
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end
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endmodule |