mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-28 07:02:55 +08:00
377 lines
14 KiB
Verilog
377 lines
14 KiB
Verilog
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`define WIDTH 16
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/* Two half adders to create a full one */
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module addsub1(
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op, oc, y, a, b, c_in,
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c_out, h_out
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);
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input op, oc; // 0: add, 1: sub
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output [`WIDTH-1:0] y;
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input [`WIDTH-1:0] a, b;
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input c_in;
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output c_out;
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output h_out;
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wire [`WIDTH/2-1:0] yh, yl;
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wire [`WIDTH/2-1:0]
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ah = a[`WIDTH-1:`WIDTH/2], al = a[`WIDTH/2-1:0];
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wire [`WIDTH/2-1:0] bh, bl;
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wire c =
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(!oc) ? 0 :
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(op) ? ~c_in : c_in;
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wire d, e;
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assign bh = (op) ? ~b[`WIDTH-1:`WIDTH/2] : b[`WIDTH-1:`WIDTH/2];
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assign bl = (op) ? ~b[`WIDTH/2-1:0] : b[`WIDTH/2-1:0];
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assign {d, yl} = al + bl + c;
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assign {e, yh} = ah + bh + d;
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assign h_out = (op) ? ~d : d;
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assign c_out = (op) ? ~e : e;
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assign y = {yh, yl};
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endmodule
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/*
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <addsub1>.
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Related source file is "C:/src/pacoblaze/pacoblaze/addsub.v".
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Found 8-bit adder carry in/out for signal <$n0001>.
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Found 8-bit adder carry in/out for signal <$n0002>.
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Found 1-bit 4-to-1 multiplexer for signal <c>.
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Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 1 Multiplexer(s).
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Unit <addsub1> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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8-bit adder carry in/out : 2
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# Multiplexers : 1
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1-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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8-bit adder carry in/out : 2
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# Multiplexers : 1
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1-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
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Optimizing unit <addsub1> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block addsub1, actual ratio is 0.
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : addsub1.ngr
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Top Level Output File Name : addsub1
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : NO
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Design Statistics
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# IOs : 53
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Cell Usage :
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# BELS : 67
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# LUT2 : 34
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# LUT3 : 1
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# MUXCY : 16
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# XORCY : 16
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# IO Buffers : 53
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# IBUF : 35
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# OBUF : 18
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s200pq208-5
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Number of Slices: 19 out of 1920 0%
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Number of 4 input LUTs: 35 out of 3840 0%
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Number of bonded IOBs: 53 out of 141 37%
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: 12.573ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 824 / 18
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-------------------------------------------------------------------------
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Delay: 12.573ns (Levels of Logic = 21)
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Source: op (PAD)
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Destination: c_out (PAD)
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Data Path: op to c_out
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 19 0.715 1.403 op_IBUF (op_IBUF)
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LUT2:I1->O 1 0.479 0.976 bl<0>1 (bl<0>)
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LUT2:I0->O 1 0.479 0.000 addsub1_yl<0>lut (N4)
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MUXCY:S->O 1 0.435 0.000 addsub1_yl<0>cy (addsub1_yl<0>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<1>cy (addsub1_yl<1>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<2>cy (addsub1_yl<2>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<3>cy (addsub1_yl<3>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<4>cy (addsub1_yl<4>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<5>cy (addsub1_yl<5>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yl<6>cy (addsub1_yl<6>_cyo)
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MUXCY:CI->O 2 0.056 0.000 addsub1_yl<7>cy (d)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<0>cy (addsub1_yh<0>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<1>cy (addsub1_yh<1>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<2>cy (addsub1_yh<2>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<3>cy (addsub1_yh<3>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<4>cy (addsub1_yh<4>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<5>cy (addsub1_yh<5>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub1_yh<6>cy (addsub1_yh<6>_cyo)
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MUXCY:CI->O 1 0.265 0.976 addsub1_yh<7>cy (e)
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LUT2:I0->O 1 0.479 0.681 c_out1 (c_out_OBUF)
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OBUF:I->O 4.909 c_out_OBUF (c_out)
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----------------------------------------
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Total 12.573ns (8.538ns logic, 4.035ns route)
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(67.9% logic, 32.1% route)
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*/
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/* Two separate adders */
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module addsub2(
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op, oc, y, yl, a, b, c_in,
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c_out, h_out
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);
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input op, oc; // 0: add, 1: sub
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output [`WIDTH-1:0] y;
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input [`WIDTH-1:0] a, b;
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input c_in;
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output c_out;
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output h_out;
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output [`WIDTH/2-1:0] yl;
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wire [`WIDTH/2-1:0]
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al = a[`WIDTH/2-1:0];
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wire [`WIDTH-1:0] bs;
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wire [`WIDTH/2-1:0] bl;
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wire c =
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(!oc) ? 0 :
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(op) ? ~c_in : c_in;
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wire d, e;
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assign bl = (op) ? ~b[`WIDTH/2-1:0] : b[`WIDTH/2-1:0];
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assign bs = (op) ? ~b : b;
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assign {d, yl} = al + bl + c;
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assign {e, y} = a + bs + c;
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assign h_out = (op) ? ~d : d;
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assign c_out = (op) ? ~e : e;
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endmodule
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/*
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <addsub2>.
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Related source file is "C:/src/pacoblaze/pacoblaze/addsub.v".
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Found 16-bit adder carry in/out for signal <$n0001>.
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Found 8-bit adder carry in/out for signal <$n0002>.
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Found 1-bit 4-to-1 multiplexer for signal <c>.
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Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 1 Multiplexer(s).
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Unit <addsub2> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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16-bit adder carry in/out : 1
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8-bit adder carry in/out : 1
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# Multiplexers : 1
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1-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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16-bit adder carry in/out : 1
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8-bit adder carry in/out : 1
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# Multiplexers : 1
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1-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
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Optimizing unit <addsub2> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block addsub2, actual ratio is 1.
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : addsub2.ngr
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Top Level Output File Name : addsub2
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : NO
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Design Statistics
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# IOs : 61
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Cell Usage :
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# BELS : 91
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# LUT2 : 34
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# LUT3 : 9
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# MUXCY : 24
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# XORCY : 24
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# IO Buffers : 61
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# IBUF : 35
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# OBUF : 26
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s200pq208-5
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Number of Slices: 23 out of 1920 1%
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Number of 4 input LUTs: 43 out of 3840 1%
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Number of bonded IOBs: 61 out of 141 43%
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: 12.955ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 1012 / 26
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-------------------------------------------------------------------------
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Delay: 12.955ns (Levels of Logic = 21)
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Source: op (PAD)
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Destination: c_out (PAD)
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Data Path: op to c_out
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 27 0.715 1.721 op_IBUF (op_IBUF)
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LUT2:I1->O 2 0.479 1.040 bs<0>1 (bs<0>)
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LUT2:I0->O 1 0.479 0.000 addsub2_y<0>lut (N4)
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MUXCY:S->O 1 0.435 0.000 addsub2_y<0>cy (addsub2_y<0>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<1>cy (addsub2_y<1>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<2>cy (addsub2_y<2>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<3>cy (addsub2_y<3>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<4>cy (addsub2_y<4>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<5>cy (addsub2_y<5>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<6>cy (addsub2_y<6>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<7>cy (addsub2_y<7>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<8>cy (addsub2_y<8>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<9>cy (addsub2_y<9>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<10>cy (addsub2_y<10>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<11>cy (addsub2_y<11>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<12>cy (addsub2_y<12>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<13>cy (addsub2_y<13>_cyo)
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MUXCY:CI->O 1 0.056 0.000 addsub2_y<14>cy (addsub2_y<14>_cyo)
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MUXCY:CI->O 1 0.265 0.976 addsub2_y<15>cy (e)
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LUT2:I0->O 1 0.479 0.681 c_out1 (c_out_OBUF)
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OBUF:I->O 4.909 c_out_OBUF (c_out)
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----------------------------------------
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Total 12.955ns (8.538ns logic, 4.418ns route)
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(65.9% logic, 34.1% route)
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*/ |