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https://github.com/pConst/basic_verilog.git
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57 lines
1.6 KiB
Plaintext
57 lines
1.6 KiB
Plaintext
/* Symbol Table */
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// counter_port = CONSTANT: 4
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// drive_wave = LABEL: 3
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// int_routine = LABEL: 688
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// interrupt_counter = REGISTER: 26
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// loop = LABEL: 5
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// pattern_10101010 = CONSTANT: 170
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// s0 = REGISTER: 0
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// s1 = REGISTER: 1
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// s2 = REGISTER: 2
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// s3 = REGISTER: 3
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// s4 = REGISTER: 4
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// s5 = REGISTER: 5
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// s6 = REGISTER: 6
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// s7 = REGISTER: 7
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// s8 = REGISTER: 8
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// s9 = REGISTER: 9
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// sA = REGISTER: 10
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// sB = REGISTER: 11
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// sC = REGISTER: 12
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// sD = REGISTER: 13
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// sE = REGISTER: 14
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// sF = REGISTER: 15
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// start = LABEL: 0
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// waveform_port = CONSTANT: 2
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/* Program Code */
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// #1: ;Interrupt example
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// #2: ;
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// #3: constant(waveform_port,2) ;bit0 will be data
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// #4: constant(counter_port,4)
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// #5: constant(pattern_10101010,170)
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// #6: register(interrupt_counter,26)
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// #7: ;
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// @000 #8: [start]
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01a00 // @000 #8: load(interrupt_counter,0) ;reset interrupt counter
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002aa // @001 #9: load(s2,pattern_10101010) ;initial output condition
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3c001 // @002 #10: interrupt(enable)
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// #11: ;
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// @003 #12: [drive_wave]
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2c202 // @003 #12: output(s2,waveform_port)
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00007 // @004 #13: load(s0,7) ;delay size
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// @005 #14: [loop]
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1c001 // @005 #14: sub(s0,1) ;delay loop
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35405 // @006 #15: jump(nz,loop)
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0e2ff // @007 #16: xor(s2,255) ;toggle waveform
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34003 // @008 #17: jump(drive_wave)
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// #18: ;
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@2b0 // #19: address(688)
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// @2b0 #20: [int_routine]
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19a01 // @2b0 #20: add(interrupt_counter,1) ;increment counter
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2da04 // @2b1 #21: output(interrupt_counter,counter_port)
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38001 // @2b2 #22: returni(enable)
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// #23: ;
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@3ff // #24: address(1023) ;set interrupt vector
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342b0 // @3ff #25: jump(int_routine)
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