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basic_verilog/scripts/opt_design.tcl
2024-03-12 17:52:08 +03:00

10 lines
404 B
Tcl

#------------------------------------------------------------------------------
# opt_design.tcl
# published as part of https://github.com/pConst/basic_verilog
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
opt_design -directive ExploreWithRemap
opt_design -aggressive_remap -resynth_remap -propconst -bufg_opt -mbufg_opt